ST STM32F301 6 Series Reference Manual page 499

RM0366
TI1
Input filter &
TIMx_CH1
edge selector
BRK
TIMx_BKIN Polarity selection
Internal break event sources
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. This signal can be used as trigger for some slave timer, see
(TIM16/TIM17).
2. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
(CSS)
- A PVD output
®
- Cortex -M4F LOCKUP (Hardfault) output
- COMP output
Figure 199. TIM16/TIM17 block diagram
Internal clock (CK_INT)
CK_PSC
PSC
CK_CNT
prescaler
C1I
TI1FP1
IC1
IC1PS
Prescaler
BI
(2)
RM0366 Rev 5
General-purpose timers (TIM15/TIM16/TIM17)
Counter Enable (CEN)
Auto-reload register
U
Stop, clear or up/down
+/-
CNT counter
U
Capture/compare 1 register
Section 19.4.23: Using timer output as trigger for other timers
Section 7.2.7: Clock security system
REP register
UI
Repetition
U
counter
DTG registers
CC1I
OC1REF
Output
OC1
DTG
control
OC1N
To other
timers for
cross-
(1)
trigerring
TIMx_CH1
TIMx_CH1N
MS31415V6
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