ST STM32F301 6 Series Reference Manual page 739

RM0366
Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.
Idle or preceding
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture strobe
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Figure 287. USART example of synchronous transmission
USART
Figure 288. USART data clock timing diagram (M bits = 00)
Start
0
LSB
Start
0
LSB
RM0366 Rev 5
RX Data out
TX Data in
Clock
CK
M bits = 00 (8 data bits)
1 2 3 4
1 2 3 4
Synchronous device
(slave SPI)
Stop
*
*
*
*
5 6 7
MSB Stop
5 6 7
MSB
*
*LBCL bit controls last data pulse
MSv31158V2
Idle or next
transmission
MSv34709V2
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