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Independent watchdog (IWDG)
23.4
IWDG registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
23.4.1
IWDG key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
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Section 1.2 on page 36
28
27
26
25
Res.
Res.
Res.
12
11
10
9
w
w
w
w
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option
is selected)
for a list of abbreviations used in register descriptions.
24
23
22
Res.
Res.
Res.
8
7
6
KEY[15:0]
w
w
w
Section 23.3.4: Register access
RM0366 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
w
w
w
w
protection)
RM0366
17
16
Res.
Res.
1
0
w
w
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