ST STM32F301 6 Series Reference Manual page 858

Debug support (DBG)
Bits 31:5 Reserved, must be kept at reset value.
Bits 4:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=1, 8,15..17)
0: The clock of the involved timer counter is fed even if the core is halted
1: The clock of the involved timer counter is stopped when the core is halted
Note: Bit1 and Bit 5 are reserved.
External PPB bus
28.15.6 TRACE pin assignment
•
Asynchronous mode
The asynchronous mode requires 1 extra pin and is available on all packages. It is only
available if using Serial Wire mode (not in JTAG mode).
TPUI pin name
TRACESWO
TPUI TRACE pin assignment
By default, these pins are NOT assigned. They can be assigned by setting the
TRACE_IOEN and TRACE_MODE bits in the MCU Debug component configuration
register. This configuration has to be done by the debugger host.
Only the asynchronous trace configuration is supported, and needs only one extra pin.
To assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and
TRACE_MODE[1:0] of the Debug MCU configuration Register (DBGMCU_CR). By default
the TRACE pins are not assigned.
858/874
Figure 342. TPIU block diagram
CLK domain
Asynchronous
ITM
FIFO
Table 124. Asynchronous TRACE pin assignment
Type
TPIU
TPIU
formatter
Trace synchronous mode
Description
O TRACE Async Data Output
RM0366 Rev 5
TRACECLKIN domain
Trace out
(serializer)
TRACESWO
STM32F3xx pin
assignment
PB3
RM0366
MS34234V1