ST STM32F301 6 Series Reference Manual page 520

General-purpose timers (TIM15/TIM16/TIM17)
The break source can be:
•
An external source connected to BKIN pin
•
An internal source:
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–
–
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Warning:
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
The break is generated by the BRK inputs which has:
•
Programmable polarity (BKP bit in the TIMx_BDTR register)
•
Programmable enable bit (BKE bit in the TIMx_BDTR register)
It is also possible to generate break events by software using BG bit in TIMx_EGR register.
When a break occurs (selected level on the break input):
•
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or even releasing the control to the GPIO (selected by the OSSI bit). This feature
functions even if the MCU oscillator is off.
•
Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control
(taken over by the GPIO) else the enable output remains high.
•
When complementary outputs are used:
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520/874
A clock failure event generated by CSS. For further information on the CSS, refer
to Section 7.2.7: Clock security system (CSS)
An output from a comparator
A PVD output
®
Cortex -M4 LOCKUP (Hardfault) output
The internal sources protection is not available when the
timer is automatic output enable mode (AOE bit set in the
TIMx_BDTR). The MOE bit is set again on the next update
event, regardless of any pending error on the BRK_ACTH
input.
The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
RM0366 Rev 5
RM0366