ST STM32F301 6 Series Reference Manual page 781

RM0366
27.3 I2S main features
• Full-duplex communication
•
Half-duplex communication (only transmitter or receiver)
• Master or slave operations
•
8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
•
Data format may be 16-bit, 24-bit, or 32-bit
•
Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
•
Programmable clock polarity (steady state)
•
Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
•
16-bit register for transmission and reception with one data register for both channel
sides
•
Supported I
–
–
–
–
•
Data direction is always MSB first
•
DMA capability for transmission and reception (16-bit wide)
•
Master clock can be output to drive an external audio component. The ratio is fixed at
256 × f
sampling frequency).
2
•
I S (I2S2 and I2S3) clock can be derived from an external clock mapped on the
I2S_CKIN pin.
27.4 SPI/I2S implementation
The following table describes all the SPI instances and their features embedded in the
devices.
Table 108. STM32F301x6/8 and STM32F318x8 SPI/I2S implementation
Enhanced NSSP & TI modes
Hardware CRC calculation
Data size configurable
2
I S support
Rx/Tx FIFO size
Wake-up capability from Low-power Sleep
Serial peripheral interface / integrated interchip sound (SPI/I2S)
2
S protocols:
2
I S Philips standard
MSB-justified standard (left-justified)
LSB-justified standard (right-justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
for all I2S modes, and to 128 x f
s
SPI
Features
for all PCM modes (where f
s
RM0366 Rev 5
is the audio
s
SPI2S2/SPI2S3
Yes
Yes
from 4 to 16 bits
Yes
32 bits
Yes
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