ST STM32F301 6 Series Reference Manual page 169

RM0366
Bits 9:8 PSIZE[1:0]: Peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1
and the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
Bit 7 MINC: Memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory
destination if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 6 PINC: Peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 5 CIRC: Circular mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
RM0366 Rev 5
Direct memory access controller (DMA)
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