ST STM32F301 6 Series Reference Manual page 505

RM0366
Figure 206. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Figure 207. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload shadow
Write a new value in TIMx_ARR
CK_PSC
CEN
31
(UIF)
FF
register
Write a new value in TIMx_ARR
CK_PSC
CEN
F0
(UIF)
F5
register
register
RM0366 Rev 5
General-purpose timers (TIM15/TIM16/TIM17)
preloaded)
32 33 34 35 36 00
preloaded)
00
F1 F2 F3 F4 F5
F5
01 02 03 04 05 06 07
36
02 05 06 07
01 03 04
36
36
MS31082V2
MS31083V2
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