ST STM32F301 6 Series Reference Manual page 347

RM0366 Advanced-control timer (TIM1)
Figure 109. Counter timing diagram, internal clock divided by N
CK_PSC
Timerclock = CK_CNT
20 1F
Counter register 01 00
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31192V1
Figure 110. Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
CEN
Timerclock = CK_CNT
06 05 04 03 02 01 00 01 02 03 04 05 06 07
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload
FD 36
register
Write a new value in TIMx_ARR
Auto-reload active
FD 36
register
MS31193V1
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