ST STM32F301 6 Series Reference Manual page 83

RM0366
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
6.3.4 Stop mode
The Stop mode is based on the Cortex-M4 deep-sleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode in the
STM32F3xx devices. In the STM32F318x8 devices, it is meaningless to distinguish
between voltage regulator in low-power mode and voltage regulator in Run mode because
the regulator is not used and V
all clocks in the 1.8 V domain are stopped, the PLL, the HSI, and the HSE RC oscillators are
disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except by a Reset. See
Section 23.3: IWDG functional description
(IWDG).
•
real-time clock (RTC): this is configured by the RTCEN bit in the
register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
register
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RTC domain control register
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable the ADC, the ADDIS bit must be set in the ADCx_CR register.
To disable the DAC, the ENx bit in the DAC_CR register must be written to 0.
Exiting Stop mode
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex-M4 System Control register.
Interrupt: refer to
None
Table 16 for details on how to enter the Stop mode.
(RCC_CSR).
Table 15. Sleep-on-exit
Description
Table 28: STM32F3xx vector
is applied externally to the regulator output. In Stop mode,
DD
in Section 23: Independent watchdog
(RCC_BDCR).
RM0366 Rev 5
Power control (PWR)
table.
Power control register
RTC domain control
Control/status
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