ST STM32F301 6 Series Reference Manual page 519

RM0366
Figure 222. Dead-time waveforms with delay greater than the positive pulse.
OCxREF
The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to
register (TIMx_BDTR)(x = 16 to 17) on page 569
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows a specific waveform to be sent (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
19.4.13 Using the break function
The purpose of the break function is to protect power switches driven by PWM signals
generated with the TIM15/TIM16/TIM17 timers. The break input is usually connected to fault
outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts
down the PWM outputs and forces them to a predefined safe state.
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to
complementary OCx and OCxN channels with break feature (TIM15) on page 547
details.
OCx
OCxN
General-purpose timers (TIM15/TIM16/TIM17)
Section 19.6.14: TIMx break and dead-time
for delay calculation.
RM0366 Rev 5
delay
Table 68: Output control bits for
MS31097V1
for more
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