ST STM32F301 6 Series Reference Manual page 195

RM0366
12.3 ADC functional description
12.3.1 ADC block diagram
Figure 24
JAUTO
ADC_JSQRx
ADC_SQRx
CONT
single/cont
V
OPAMPx
V
TS
V
REFINT
V
V
BAT INP[18:1]
ADC_IN
V
INN[18:1]
[15:1]
analog input
V channels
REF-
AUTDLY
auto delayed
ADSTP
stop conv
EXT0
EXT1
EXT2
.......
.......
EXT13
EXT14
EXT15
EXTi mapped at
product level
JEXT0
JEXT1
JEXT2
.......
.......
JEXT13
JEXT14
JEXT15
JEXTi mapped at
product level
shows the ADC block diagram and
Figure 24. ADC block diagram
Analog Supply (VDDA)
1.8V to 3.6 V
autopower-down
ADCAL
self calibration
Input
selection &
scan control
SMPx[2:0]
sampling time
Start & Stop
Control
S/W trigger
h/w
trigger
EXTEN[1:0]
trigger enable
and edge selection
EXTSEL[3:0]
trigger selection
J
S/W trigger
H/W
trigger
JEXTEN[1:0]
trigger enable
and edge selection
JEXTSEL[3:0]
trigger selection
Table 31
V
REF+
1.8 to 3.6 V
RDATA[11:0]
JDATA1[11:0]
JDATA2[11:0]
JDATA3[11:0]
JDATA4[11:0]
Bias & Ref
SAR ADC
V
IN
CONVERTED
DATA
start
OVRMOD
overrun mode
ALIGN
left/right
RES[1:0]
12, 10, 8 bits
JOFFSETx[11:0]
JOFFSETx_CH[11:0]
DISCEN
DISCNU[:0]
Discontinuous
mode
AWD1EN
JAWD1EN
AWD1SGL
AWDCH1[4:0]
JDISCEN
JDISCNUM[2:0]
LT1[11:0]
HT1[11:0]
JQM
AWDCH2[18:0]
Injced Context
Queue Mode
LT2[7:0]
AWDCH3[18:0]
HT2[7:0]
HT3[7:0]
LT3[7:0]
RM0366 Rev 5
Analog-to-digital converters (ADC)
gives the ADC pin description.
AREADY
EOSMP
ADC Interrupt
EOC
EOS
OVR
JEOS
JQOVF
slave
AWDx
AHB
interface
DMA request
DMACFG
DMAEN
Analog watchdog 1,2,3
AWD1_OUT
AWD1
AWD2_OUT
AWD2
AWD3_OUT
AWD3
Cortex
M4 with
FPU
IRQ
master
master
DMA
TIMERs
ETR
MSv30260V3
195/874
277