ST STM32F301 6 Series Reference Manual page 87

RM0366
6.4 Power control registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
6.4.1 Power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by wake-up from Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Bit 8 DBP: Disable RTC domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write
access. This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set
to 1.
Bits 7:5 PLS[2:0]: PVD level selection.
These bits are written by software to select the voltage threshold detected by the
programmable voltage detector.
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
Notes:
1. Refer to the electrical characteristics of the datasheet for more details.
2. Once the PVD_LOCK is enabled (for CLASS B protection) the PLS[2:0] bits
cannot be programmed anymore.
Bit 4 PVDE: Programmable voltage detector enable.
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
24 23 22
Res. Res. Res.
8 7 6
DBP PLS[2:0]
rw rw rw
RM0366 Rev 5
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PVDE CSBF CWUF
rw rw rc_w1 rc_w1
17 16
Res. Res.
1 0
PDDS LPDS
rw rw
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