ST STM32F301 6 Series Reference Manual page 254

Analog-to-digital converters (ADC)
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to
data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN)
0: Right alignment
1: Left alignment
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit
01: 10-bit
10: 8-bit
11: 6-bit
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is effective
only when DMAEN=1.
0: DMA One Shot Mode selected
1: DMA Circular Mode selected
For more details, refer to
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the GP-DMA to manage automatically the converted data. For more details, refer to
Managing conversions using the
0: DMA disabled
1: DMA enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
12.5.5 ADC sample time register 1 (ADCx_SMPR1, x=1)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
Res. Res. SMP9[2:0]
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15 14 13 12
SMP
SMP4[2:0]
5_0
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254/874
Section : Managing conversions using the DMA
DMA.
27 26 25 24
SMP8[2:0]
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11 10 9 8
SMP3[2:0]
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RM0366 Rev 5
23 22 21
SMP7[2:0]
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7 6 5
SMP2[2:0] SMP1[2:0]
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Figure : Data register,
Section :
20 19 18 17
SMP6[2:0] SMP5[2:1]
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4 3 2 1
Res. Res.
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RM0366
16
rw
0
Res.