ST STM32F301 6 Series Reference Manual page 658

Inter-integrated circuit interface (I2C)
Transmission
If the I2C_TXDR register is not empty (TXE = 0), its content is copied into the shift register
after the ninth SCL pulse (the acknowledge pulse). Then the shift register content is shifted
out on the SDA line. If TXE = 1, which means that no data is written yet in I2C_TXDR, the
SCL line is stretched low until I2C_TXDR is written. The stretch starts after the ninth SCL
pulse.
Shift register
I2C_TXDR
Hardware transfer management
The I2C features an embedded byte counter to manage byte transfer and to close the
communication in various modes, such as:
–
–
–
In controller mode, the byte counter is always used. By default, it is disabled in target mode.
It can be enabled by software, by setting the SBC (target byte control) bit of the I2C_CR1
register.
The number of bytes to transfer is programmed in the NBYTES[7:0] bitfield of the I2C_CR2
register. If this number is greater than 255, or if a receiver wants to control the acknowledge
value of a received data byte, the reload mode must be selected, by setting the RELOAD bit
of the I2C_CR2 register. In this mode, the TCR flag is set when the number of bytes
programmed in NBYTES[7:0] is transferred (when the associated counter reaches zero),
and an interrupt is generated if TCIE is set. SCL is stretched as long as the TCR flag is set.
TCR is cleared by software when NBYTES[7:0] is written to a non-zero value.
When NBYTES[7:0] is reloaded with the last number of bytes to transfer, the RELOAD bit
must be cleared.
658/874
Figure 251. Data transmission
ACK pulse
SCL
xx
TXE
data0
NACK, STOP and ReSTART generation in controller mode
ACK control in target receiver mode
PEC generation/checking
xx
wr data1 wr data2
data1
RM0366 Rev 5
ACK pulse
xx
data2
RM0366
legend:
SCL
stretch
MS19849V1