ST STM32F301 6 Series Reference Manual page 171

RM0366
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer (0 to 2
This bitfield is updated by hardware when the channel is enabled:
If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This bitfield is set and cleared by software. It must not be written when the channel is
10.6.5 DMA channel x peripheral address register (DMA_CPARx)
Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 PA[31:0]: Peripheral address
It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1
and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if
DIR = 1 and the peripheral source address if DIR = 0.
Note: This bitfield is set and cleared by software. It must not be written when the channel is
– It is decremented after each single DMA 'read followed by write' transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
28 27 26 25
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12 11 10 9
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enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
Direct memory access controller (DMA)
16
- 1)
24 23 22
PA[31:16]
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8 7 6
PA[15:0]
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RM0366 Rev 5
21 20 19 18
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5 4 3 2
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17 16
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1 0
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