ST STM32F301 6 Series Reference Manual page 819

RM0366
Where F
provided to the SPI/I2S block.
Note: I2SDIV must be strictly higher than 1.
The following table provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.
Table 110. Audio-frequency precision using standard 8 MHz HSE
I2S_DIV
SYSCLK
(MHz)
16-bit 32-bit
72 11
72 23
72 25
72 35
72 51
72 70
72 102
72 140
72 3
72 3
72 9
72 6
72 9
72 13
72 17
1. This table gives only example values for different clock configurations. Other configurations allowing optimum clock
precision are possible.
2
27.7.6 I S master mode
The I2S can be configured as follows:
•
In master mode for transmission or reception (half-duplex mode using I2Sx)
• In master mode transmission and reception (full-duplex mode using I2Sx and
I2Sx_ext).
This means that the serial clock is generated on the CK pin as well as the Word Select
signal WS. Master clock (MCK) may be output or not, controlled by the MCKOE bit in the
SPIx_I2SPR register.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
is the audio sampling frequency, and F
S
I2S_ODD
16-bit 32-bit
6 1 0
11 1 1
13 1 0
17 0 1
25 0 1
35 1 0
51 0 0
70 1 1
3 0 0
3 0 0
9 0 0
6 1 1
9 0 0
13 0 0
17 1 1
I2SxCLK
Target f
S
MCLK
(Hz)
16-bit
No 96000 97826.09
No 48000 47872.34
No 44100 44117.65
No 32000 32142.86
No 22050 22058.82
No 16000 15675.75
No 11025 11029.41
No 8000 8007.11
Yes 48000 46875
Yes 44100 46875
Yes 32000 31250
Yes 22050 21634.61
Yes 16000 15625
Yes 11025 10817.30
Yes 8000 8035.71
RM0366 Rev 5
is the frequency of the kernel clock
(1)
Real f (KHz)
S
32-bit 16-bit
93750 1.90%
48913.04 0.27%
43269.23 0.04%
32142.86 0.44%
22058.82 0.04%
16071.43 0.27%
11029.41 0.04%
7978.72 0.09%
46875 2.34%
46875 6.29%
31250 2.34%
21634.61 1.88%
15625 2.34%
10817.30 1.88%
8035.71 0.45%
Error
32-bit
2.34%
1.90%
1.88%
0.44%
0.04%
0.45%
0.04%
0.27%
2.34%
6.29%
2.34%
1.88%
2.34%
1.88%
0.45%
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