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ST STM32F301 6 Series Reference Manual page 265

Advanced arm-based 32-bit mcus

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RM0366
12.5.15
ADC injected sequence register (ADCx_JSQR, x=1)
Address offset: 0x4C
Reset value: 0x0000 0000
31
30
29
Res.
JSQ4[4:0]
rw
rw
15
14
13
JSQ2[1:0]
Res.
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence
These bits are written by software with the channel number (1..18) assigned as the 4th in the
injected conversion sequence.
Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1).
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 25 Reserved, must be kept at reset value.
Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence
These bits are written by software with the channel number (1..18) assigned as the 3rd in the
injected conversion sequence.
Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1).
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 19 Reserved, must be kept at reset value.
Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence
These bits are written by software with the channel number (1..18) assigned as the 2nd in the
injected conversion sequence.
Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1).
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 13 Reserved, must be kept at reset value.
Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence
These bits are written by software with the channel number (1..18) assigned as the 1st in the
injected conversion sequence.
Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1).
Note: Analog input channel 0 is not mapped: value "00000" should not be used
28
27
26
25
Res.
rw
rw
rw
12
11
10
9
JSQ1[4:0]
rw
rw
rw
rw
24
23
22
JSQ3[4:0]
rw
rw
rw
8
7
6
JEXTEN[1:0]
rw
rw
RM0366 Rev 5
Analog-to-digital converters (ADC)
21
20
19
18
Res.
rw
rw
rw
5
4
3
2
JEXTSEL[3:0]
rw
rw
rw
rw
17
16
JSQ2[4:2]
rw
rw
1
0
JL[1:0]
rw
rw
265/874
277

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Stm32f301 8 seriesStm32f318 8 series