ST STM32F301 6 Series Reference Manual page 115

RM0366
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
Bits 27:23 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
Bit 17 USART2EN: USART2 clock enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
Bits 10:5 Reserved, must be kept at reset value.
0: Power interface clock disabled
1: Power interface clock enabled
0: I2C2 clock disabled
1: I2C2 clock enabled
0: I2C1 clock disabled
1: I2C1 clock enabled
0: USART3 clock disabled
1: USART3 clock enabled
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
0: SPI3 clock disabled
1: SPI3 clock enabled
0: SPI2 clock disabled
1: SPI2 clock enabled
0: Window watchdog clock disabled
1: Window watchdog clock enabled
RM0366 Rev 5
Reset and clock control (RCC)
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