ST STM32F301 6 Series Reference Manual page 104

Reset and clock control (RCC)
7.4.2 Clock configuration register (RCC_CFGR)
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
PLLNO
MCOPRE[2:0]
DIV
rw rw rw
15 14 13
Res. Res. PPRE2[2:0]
rw
Bit 31 PLLNODIV: Do not divide PLL to MCO
This bit is set and cleared by software. It switch-off divider-by-2 for PLL connection to MCO
0: PLL is divided by 2 before MCO
1: PLL is not divided before MCO
Bits 30:28 MCOPRE[2:0]: Microcontroller Clock Output Prescaler
There bits are set and cleared by software. It is highly recommended to change this prescaler
before MCO output is enabled
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 MCO[2:0]: Microcontroller clock output
Set and cleared by software.
Note: This clock output may have some truncated cycles at startup or during MCO clock
Bit 23 I2SSRC: I2S external clock source selection
Set and reset by software to clock I2S2 and I2S3 with an external clock. This bits must be
valid before enabling I2S2-3 clocks.
Bit 22 Reserved, must be kept at reset value.
104/874
wait state 2, word, half-word and byte access
≤ ≤
28 27 26 25
Res. MCO[2:0]
rw rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
.....
111: MCO is divided by 128
000: MCO output disabled, no clock on MCO
001: Reserved
010: LSI clock selected.
011: LSE clock selected.
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock selected (divided by 1 or 2 depending on PLLNODIV bit).
source switching.
0: I2S2 and I2S3 clocked by system clock
1: I2S2 and I2S3 clocked by the external clock
24 23 22
I2SSRC Res.
rw rw
8 7 6
HPRE[3:0]
rw rw rw
RM0366 Rev 5
21 20 19 18
PLLMUL[3:0]
rw rw rw rw
5 4 3 2
SWS[1:0]
rw rw r r
RM0366
17 16
PLL PLL
XTPRE SRC
rw rw
1 0
SW[1:0]
rw rw