ST STM32F301 6 Series Reference Manual page 322

Touch sensing controller (TSC)
Bits 31:28 CTPH[3:0]: Charge transfer pulse high
Note: These bits must not be modified when an acquisition is ongoing.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Refer to the
Bits 23:17 SSD[6:0]: Spread spectrum deviation
Note: These bits must not be modified when an acquisition is ongoing.
Bit 16 SSE: Spread spectrum enable
Note: This bit must not be modified when an acquisition is ongoing.
Bit 15 SSPSC: Spread spectrum prescaler
Note: This bit must not be modified when an acquisition is ongoing.
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These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of C
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from C
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
acquisition sequence
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of periods of the SSCLK clock to the charge transfer
pulse high state.
0000000: 1x t
SSCLK
0000001: 2x t
SSCLK
...
1111111: 128x t
SSCLK
This bit is set and cleared by software to enable/disable the spread spectrum feature.
0: Spread spectrum disabled
1: Spread spectrum enabled
This bit is set and cleared by software. It selects the AHB clock divider used to generate the
spread spectrum clock (SSCLK).
0: f
HCLK
1: f /2
HCLK
).
X
to C
X
for details.
RM0366 Rev 5
).
S
Section 16.3.4: Charge transfer
RM0366