ST STM32F301 6 Series Reference Manual page 582

Basic timers (TIM6)
Figure 240. Control circuit in normal mode, internal clock divided by 1
CEN=CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
20.3.5 Debug mode
When the microcontroller enters the debug mode (Cortex
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to
support for timers, watchdog I
20.4 TIM6 registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
20.4.1 TIM6 control register 1 (TIM6_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bits 10:8 Reserved, must be kept at reset value.
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Internal clock
UG
CNT_INIT
31
2
Section 1.2 on page 36
12 11 10 9
UIFRE
Res. Res.
MAP
rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
3 2 33 34 35 36
C.
for a list of abbreviations used in register descriptions.
8 7 6
Res. ARPE Res.
rw
RM0366 Rev 5
00 01 02 03 04 05
®
-M4F core - halted), the TIMx
Section 28.15.2: Debug
5 4 3 2
Res. Res. OPM URS
rw rw
RM0366
06 07
MS31085V2
1 0
UDIS CEN
rw rw