ST STM32F301 6 Series Reference Manual page 478

General-purpose timer (TIM2)
18.4.4 TIM2 DMA/Interrupt enable register (TIM2_DIER)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. TDE Res. CC4DE CC3DE CC2DE CC1DE
rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
Bit 8 UDE: Update DMA request enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
478/874
12 11 10 9
rw rw rw rw
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
0: Update DMA request disabled.
1: Update DMA request enabled.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
8 7 6
UDE Res. TIE
rw rw
RM0366 Rev 5
5 4 3 2
Res. CC4IE CC3IE CC2IE
rw rw rw
RM0366
1 0
CC1IE UIE
rw rw