ST STM32F301 6 Series Reference Manual page 375

RM0366
Counter (CNT)
(OCxCE = '0')
(OCxCE = '1')
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
Figure 137. Clearing TIMx OCxREF
(CCRx)
ETRF
OCxREF
OCxREF
ocref_clr_int ocref_clr_int
becomes high
RM0366 Rev 5
Advanced-control timer (TIM1)
still high
MS33105V2
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