I 2 C0 Control Register 0 (S1D0 Register); Bits 0 To 2: Bit Counter (Bc0-Bc2); Bit 3: I2C Interface Enable Bit (Es0); Bit 4: Data Format Select Bit (Als) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
2
16.4 I C0 Control Register 0 (S1D0 register)
2
The I C0 control register 0 (address 02E3
16.4.1 Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. The I
interrupt request signal is generated immediately after the number of count specified with these bits (the
ACK clock is added to the number of count when the ACK clock is selected by the ACK bit (bit 7 of address
02E4 )) have been transferred, and the BC0 to BC2 are returned to "000
16
Also when a START condition is detected, these bits become "000
transmitted and received in 8 bits.
2
16.4.2 Bit 3: I
This bit enables to use the multi-master I
disabled and the S
enabled.
When the ES0 bit is set to "0", the following is performed.
1)Set MST = 1, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0, and ADR0 = 0, of the I
register (Address : 02E8
2)Writing the data into the I
3)The TOF bit in the I
2
4)The I C system clock (V

16.4.3 Bit 4: Data format select bit (ALS)

This bit decides if the recognition of the slave address is processed or not. When this bit is set to "0", the
addressing format is selected and the address data is recognized. The transfer will be processed only
when a comparison is matched between the slave address and the address data or a general call is
received (Refer to Figure 16.5 I
this bit is set to "1", the free data format is selected and the slave address is not recognized.
2
16.4.4 Bit 6: I
The bit is used to reset the I
When the ES0 bit is "1" (I
Flags are processed as follows:
1)Set MST = 0, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0, and ADR0 = 0, of I
register (Address : 02E8
2)The TOF bit of the I
3)The internal counter, flags are initialized.
After writing"1" to the IHR bit, the circuit reset processing is finished in Max. 2.5 V
bit is automatically cleared to "0". Figure 16.10 shows the reset timing.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
C interface enable bit (ES0)
and the S become high-impedance. When the bit is set to "1", the interface is
DA CL
)
16
2
C0 data shift register (Address : 02E0
2
C0 control register (Address : 02E7
) is stopped and the internal counter, flags are initialized.
IIC
2
C0 status register: the item of bit 1, general call detection flag). When
C bus interface reset bit (IHR)
2
C bus interface circuit when the abnormal communication occurs.
2
C bus interface is enabled), writing "1" to the IHR bit resets H/W.
)
16
2
C0 control register 2 (Address : 02E7
page 259 of 402
) controls the data communication format.
16
2
C bus interface. When this bit is set to "0", the interface is
) is cleared to "0"
16
) is cleared to "0"
16
2
16. MULTI-MASTER I C bus INTERFACE
2
".
2
" and the address data is always
2
) is disabled.
16
2
C0 status
cycles and the IHR
IIC
C bus interface
2
C0 status