Pin Assignment Control Register (Pacr); Digital Debounce Function - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

17.5 Pin Assignment Control Register (PACR)

Figure 17.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before
a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function
as I/O ports.
Bits PACR2 to PACR0: control pins to be used
Value after reset: 000
To select the 80-pin package, set the bits to 011
To select the 64-pin package, set the bits to 010
U1MAP bit: controls pin assignments for the UART1 function.
To assign the UART1 function to P6
bit to 0 (P6 to P6 ).
7 4
To assign the function to P7
(P7 to P7 )
3 0
The PRC2 bit in the PRCR protects the PACR register. Set the PACR register after setting the PRC2 bit in
the PRCR register.

17.6 Digital Debounce Function

Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Figure 17.11 shows the NDDR register and the P17DDR register.
Additionally, a digital debounce function is disabled to the port P1
Filter width : (n+1) x 1/f8
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or a
rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 00
function. Setting to FF
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
.
2
/CTS
4
/CTS /RTS
0 1
________
n: count value set in the NDDR register and P17DDR register
disables the digital filter. See Figure 17.12 for details.
16
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f o 3 8 5
.
2
.
2
/RTS , P6 /CLK , P6
1 1 5 1
, P7 /CLK , P7 /RxD
1 1 1 2 1
_______ _____
7
to FF
16
17. Programmable I/O Ports
/RxD , and P6 /TxD
6 1 7 1
, and P7 /TxD , set the U1MAP bit to 1
3 1
input and the port P8
5
when using the digital debounce
16
, set the U1MAP
input.