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Texas Instruments TMS370 Series Application Book

Texas Instruments TMS370 Series Application Book

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TMS370 Microcontroller Family

1996

Application

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8-Bit Microcontroller Family

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Page 1 TMS370 Microcontroller Family Application Book 1996 8-Bit Microcontroller Family...
Page 2 Printed in U.S.A., February 1996 SPNA017...
Page 3 TMS370 Microcontroller Family Application Book...
Page 4 TMS370 Microcontroller Family Application Book Microcontroller Products—Semiconductor Group SPNA017 February 1996...
Page 5 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
Page 6: Table Of Contents
Contents Part I: Introduction Introduction ..............Overview .
Page 7 Table Search With the TMS370 ..........Bubble Sort With the TMS370 .
Page 8 The SCI – How It Works ............Choosing SCI Protocols and Formats .
Page 9 Fast Method to Determine Parity ..........Automatic Baud Rate Calculation .
Page 10 Display Dimming Application Routine ......... . . Speedometer and Tachometer Display Application .
Page 11 Appendix B: A / D Errors ............Appendix C: External A / D Converters .
Page 12 I/O Pins Proper Termination of Unused I/O Pins ........Introduction .
Page 13 ..............Cost Effective Input Protection Circuitry for the Texas Instruments...
Page 14 Advantages of Internal Diode Protection Circuitry ........Designing Input Protection Circuitry for TMS370 Microcontrollers .
Page 15 List of Illustrations Binary Division With the TMS370 ..........1.
Page 16 16. Flowchart for Time of Day Clock Application ........17.
Page 17 ............Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers .
Page 18 Indeterminate Range for TTL and CMOS Input Thresholds (V = 5 V) ..........Switching to Vehicle Battery (Vbat) .
Page 19 ......... . . Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers .
Page 20: Part I: Introduction
Part I Introduction...
Page 22 Introduction Microcontroller Products—Semiconductor Group Texas Instruments...
Page 24: Introduction
Overview The TMS370 family consists of VLSI, 8-bit, CMOS microcontrollers with on-chip EEPROM storage and peripheral support functions. These devices offer superior performance in complex, real-time control applications in demanding environments. They are available with mask-programmable ROM and EPROM. Robust features in the TMS370 family of devices enhance performance and enable new application technologies.
Page 26: Part Ii: Software Routines
Part II Software Routines Part II contains three sections: Arithmetic ......Memory Operations ....Specific Functionality .
Page 28: 16 16 (32-Bit) Multiplication
16 16 (32-Bit) Multiplication With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 30 16 16 (32-Bit) Multiplication This example multiplies the 16-bit value in register pair R2, R3 by the value in register pair R4, R5. The results are stored in R6, R7, R8, R9; registers A and B are altered. Routine ******************************************************** 16-BIT MPY: X VALUE Y VALUE...
Page 32: Binary Division With The Tms370
Binary Division With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 34: Divide 16 Bit Number By 8 Bit Number
Divide 16-Bit Number by 8-Bit Number This routine divides a 16-bit number concatenated in R1:R2 by an 8-bit number in R3 to give a 16-bit quotient and an 8-bit remainder as shown in Figure 1. This routine uses the DIV instruction (note that a DIV function provides maximum values of 8-bits, 255 , for both quotient and remainder).
Page 35: Divide 16 Bit Number By 16 Bit Number
Divide 16-Bit Number by 16-Bit Number This program divides a 16-bit dividend by a 16-bit divisor and produces a 16-bit quotient with a 16-bit remainder. All numbers are unsigned positive integers and can range from 0 to FFFFh. The same principle can be applied to larger or smaller divide routines to allow different-sized quotients, dividends, divisors, and remainders.
Page 36: Bcd-To-Binary Conversion On The Tms370
BCD-to-Binary Conversion on the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 38 BCD-to-Binary Conversion This routine converts a four-digit BCD number to binary. The maximum BCD number is 9999 decimal. Operands originate and are stored in general-purpose RAM. The BCD number is composed of the four digits (D3, D2, D1, and D0) contained in the bytes DH and DL. The binary number is calculated by dividing the number into powers of ten (Binary = D3 1000 + D2 100 + D1 10 + D0 1).
Page 40: Binary-To-Bcd Conversion On The Tms370
Binary-to-BCD Conversion on the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 42: Register Values
Binary-to-BCD Conversion This program converts a 16-bit binary word (0 to 65.535) to a packed six-nibble BCD value. Table 1. Register Values Register Before After BCD MSbyte BCD LSbyte BINARY MSbyte ZERO BINARY LSbyte ZERO ZERO Routine .TEXT 7000H ;Absolute start address BN2BCD ;Prepare answer registers #16,R5...
Page 44: Bcd String Addition With The Tms370
BCD String Addition With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 46: Register Values And Functions
BCD String Addition The following routine uses the addition instruction to add two multi-digit numbers together. Each number is a packed BCD string of less than 256 bytes (512 digits), stored at memory locations STR1 and STR2. This routine adds the two strings together and places the result in STR2. The strings must be stored with the most significant byte in the lowest numbered register.
Page 48: Tms370 Floating Point Package
TMS370 Floating Point Package Microcontroller Products—Semiconductor Group Texas Instruments...
Page 50: Introduction
Introduction This report describes assembly language floating point math routines for the TMS370 family of microcontrollers. Floating point operations allow binary processors to carry out decimal, signed arithmetic. This package includes most of the common arithmetic and conversion routines used in floating point operations.
Page 51: Floating Point Format
Floating Point Format Each number in this floating point format is 24 bits long. This includes eight bits for the exponent, fifteen for the mantissa, and the remaining bits for the sign. The format is as follows: E E E E E E E E S M M M M M M M M M M M M M M M The first byte is devoted to the exponent.
Page 52: Floating Point Routines
Floating Point Routines Floating Point Addition / Subtraction ;Rev.1.0 ;Function name $fp_add,$fp_sub ;Purpose 1) Perform the addition of two floating point numbers. OP1 + OP2 2) Perform the subtraction of two floating point numbers. OP1 - OP2 ;Registers used Register Before After -------------------------------------------------------...
Page 53 2) If an operation results in a sum or difference which is greater than MAX_POS, then it is overflow. The result placed in registers R17, R18, R19 will be MAX_POS. 3) If an operation results in a sum or difference which is less than MAX_NEG, then it is overflow.
Page 54 negneg #80h,a ;Eventual sign negative cont negpos #82h,a ;Result negative, set subtract flag. cont pospos ;Eventual sign positive cont #80h,msb1 ;Set the implied one. #80h,msb2 #0h,b noshift loop clrc msb1 ;Align the smaller mantissa. lsb1 djnz b,loop noshift jbit1 subflag,sub lsb1,lsb2 ;Add the mantissas.
Page 55 maxval #0ffh,exp2 ;Create maximum value. movw #07fffh,lsb2 a,msb2 ;Set sign bit as appropriate.
Page 56: Floating Point Number Comparison
Floating Point Number Comparison ;Rev.1.0 ;Function name $fp_cmp ;Purpose Perform a comparison of two floating point numbers. The routine compares OP2 to OP1 and sets the status bits. The status result of this routine will be equivalent to an 8-bit integer cmp such as: OP1,OP2.
Page 57 $fp_cmp PUSH msb2 ;Check for different sign first. msb1,msb2 BTJZ #080h,msb2,SAMESIGN ;If MSB is 0, operands have same sign. msb2 ;Operands have different sign. Test ;MSB2 to check sign. Make ;appropriate dummy move to set NONEG ;status. SAMESIGN POP msb2 ;Restore MSB2 exp1,exp2 ;OP1 >...
Page 58: Floating Point Division
Floating Point Division ;Rev.1.0 ;Function name $fp_div ;Purpose Perform the division of two floating point numbers OP1 / OP2 ;Registers used Register Before After ------------------------------------------------------- Status | Modified OP1 exponent Modified OP1 mantissa MSB Modified OP1 mantissa LSB Modified OP2 exponent Result exponent OP2 mantissa MSB Result mantissa MSB...
Page 59 ;Stack space 4 bytes ;Notes 1) Some special considerations for floating point divide are: ZERO ZERO ZERO MAX_POS (if OP1 >= 0) MAX_NEG (if OP1 < 2) If a division results in a quotient which is greater than MAX_POS, then it is overflow. The result placed in registers R17, R18, R19 will be MAX_POS.
Page 60 FINDSIGN PUSH ;Save registers. PUSH COUNTER PUSH FLAGS MAN1MSB,FLAGS ;Find sign of quotient. MAN2MSB,FLAGS ;If sign flags differ, FLAGS 7=1. #080h,FLAGS ;Clear other bits in FLAGS. #080h,MAN1MSB ;Set implied 1 in sign bit position. #080h,MAN2MSB SUBEXP ;Clear B for result of exponent math. EXP2,EXP1 ;Subtract exponents.
Page 61 DIVEND DJNZ COUNTER,DIVIDE ;Next bit. Is divide done? ;Finish last rotate. DONE ;If MSB is not one, decrement EXP2 #01h,EXP2 ;and go back up and shift one more ;time. UNDERFLOW ;If EXP2 was zero, decrement has ;caused an underflow. SBIT0 OVFL ;Clear flag to show possible overflow ;condition has been corrected.
Page 62: Floating Point Multiplication
Floating Point Multiplication ;Rev.1.0 ;Function name $fp_mul ;Purpose Perform the multiplication of two floating point numbers. OP1 * OP2 ;Registers used Register Before After ------------------------------------------------------- Status | Modified OP1 exponent Modified OP1 mantissa MSB Modified OP1 mantissa LSB Modified OP2 exponent Result exponent OP2 mantissa MSB Result mantissa MSB...
Page 63 .global $fp_mul $fp_mul ;Check for OP1=ZERO. BTJO #0FFh,EXP2,CHK_OP2 BTJO #0FFh,MAN1LSB,CHK_OP2 BTJO #0FFh,MAN1MSB,CHK_OP2 MAN2LSB ;OP1 is ZERO, so clear OP2 as answer. MAN2MSB EXP2 ;Exit fp_mul CHK_OP2 ;Check for OP2=ZERO BTJO #0FFh,EXP2,FINDSIGN BTJO #0FFh,MAN2LSB,FINDSIGN BTJO #0FFh,MAN2MSB,FINDSIGN ;OP2 is ZERO, so done. Exit fp_mul.
Page 64 CHK_UNDER ;Addition of exponents has ;underflowed. BTJZ #0FFh,EXP2,UNDERFLOW ;If exponent is not FF, then the ;exponent has definitely ;underflowed. SBIT1 UNDER_BIT ;Set bit to indicate that an ;underflow is possible if not ;corrected at end of multiplication ;routine. MULTIPLY PUSH ;Save value of B register.
Page 65: Floating Point Increment / Decrement
Floating Point Increment / Decrement ;Rev.1.0 ;Function name $fp_inc,$fp_dec ;Purpose 1) Increment a floating point number, i.e. add a 1.0 to it. OP1 + 1.0 2) Decrement a floating point number, i.e. subtract 1.0 from it. OP1 - 1.0 ;Registers used Register Before After...
Page 66 $fp_inc ;Entry point for increment. push ;Save A register. msb1,a ;Move msb1 to A register and set every #07fh,a ;bit except sign bit. #90h,exp1 ;Check to see if 1.0 is insignificant done ;compared with size of OP1. Exit if ;OP1 will not change. #71h,exp1 ;Check to see if OP1 is insignificant size_ok...
Page 67 adjust exp1 ;Shift the mantissa and adjust the clrc ;exponent until an implied one is set. lsb1 msb1 adjust done2 greater lsb2 ;OP1 is greater than 1. Shift 1 so it msb2 ;has the same exponent as OP1. If the #07h,b ;exponents differ by <...
Page 68: Floating Point Number Test
Floating Point Number Test ;Rev.1.0 ;Function name $fp_tst ;Purpose Perform a test of the floating point number, similar to the hardware TST instruction for the A and B registers. ;Registers used Register Before After ------------------------------------------------------- Status | Set on result OP1 exponent OP1 exponent OP1 mantissa MSB...
Page 69: Floating Point Number Negation
Floating Point Number Negation ;Rev.1.0 ;Function name $fp_neg ;Purpose Perform the sign negation of a floating point number -OP1 ;Registers used Register Before After ------------------------------------------------------- Status | Set on result MSB OP1 exponent Result exponent OP1 mantissa MSB Result mantissa MSB OP1 mantissa LSB Result mantissa LSB ;Size...
Page 70: Floating Point To Signed 8-Bit Integer Conversion
Floating Point To Signed 8-Bit Integer Conversion ;Rev.1.0 ;Function name $fp_ftoi ;Purpose Convert a 24-bit signed floating representation of a number to an equivalent 8-bit signed integer representation. ;Registers used Register Before After ------------------------------------------------------- Status | Modified Result OP2 exponent OP2 exponent OP2 mantissa MSB OP2 mantissa MSB...
Page 71 bigminus ;Number is too small to be represented as a #80h,a ;signed integer. Set result to max negative ;value.
Page 72: Floating Point To Signed Long (16-Bit) Integer Conversion
Floating Point To Signed Long (16-Bit) Integer Conversion ;Rev.1.0 ;Function name $fp_ftol ;Purpose Convert a 24-bit signed floating representation of a number to an equivalent 16-bit signed integer representation. ;Registers used Register Before After ------------------------------------------------------- Status | Modified Signed integer MSB Signed integer LSB OP1 exponent OP1 exponent...
Page 73 expon jbit1 fsign,bigminus #0ffh,b ;Number is too big to be represented as a ;signed integer. #7fh,a ;Set result to max positive value. bigminus #0,b ;Number is too small to be represented as a #80h,a ;signed integer. Set result to max negative ;value.
Page 74: Floating Point To Unsigned 8-Bit Integer Conversion
Floating Point To Unsigned 8-Bit Integer Conversion ;Rev.1.0 ;Function name $fp_ftou ;Purpose Convert a 24-bit signed floating representation of a number to an equivalent 8-bit unsigned integer representation. ;Registers used Register Before After ------------------------------------------------------- Status | Modified Result OP1 exponent OP1 exponent OP1 mantissa MSB OP1 mantissa MSB...
Page 75: Floating Point To Unsigned Long (16-Bit) Integer Conversion
Floating Point To Unsigned Long (16-Bit) Integer Conversion ;Rev.1.0 ;Function name $fp_ftoul ;Purpose Convert a 24-bit signed floating representation of a number to an equivalent 16-bit unsigned integer representation. ;Registers used Register Before After ------------------------------------------------------- Status | Modified Signed integer MSB Signed integer LSB OP1 exponent OP1 exponent...
Page 76: Signed 8-Bit Integer To Floating Point Conversion
Signed 8-Bit Integer To Floating Point Conversion ;Rev.1.0 ;Function name $fp_itof ;Purpose Convert an 8-bit signed integer representation of a number to an equivalent 24-bit signed floating point representation. ;Registers used Register Before After ------------------------------------------------------- Status | Set on Result Signed integer Modified Result exponent...
Page 77: Signed Long (16-Bit) Integer To Floating Point Conversion Comparison
Signed Long (16-Bit) Integer To Floating Point Conversion Comparison ;Rev.1.0 ;Function name $fp_ltof ;Purpose Convert a 16-bit signed long integer representation of a number to an equivalent 24-bit signed floating point representation. ;Registers used Register Before After ------------------------------------------------------- Status | Set on result MSB Signed integer MSB | Modified...
Page 78: Unsigned Long (16-Bit) Integer To Floating Point Conversion
Unsigned Long (16-Bit) Integer To Floating Point Conversion ;Rev.1.0 ;Function name $fp_ultof ;Purpose Convert a 16-bit unsigned long integer representation of a number to an equivalent 24-bit signed floating point representation. ;Registers used Register Before After ------------------------------------------------------- Status | | Set on status of MSB Integer MSB Integer LSB Result exponent...
Page 79: Unsigned 8-Bit Integer To Floating Point Conversion
Unsigned 8-Bit Integer To Floating Point Conversion ;Rev.1.0 ;Function name $fp_utof ;Purpose Convert an 8-bit unsigned integer representation of a number to an equivalent 24-bit signed floating point representation. ;Registers used Register Before After ------------------------------------------------------- Status | | Set on status of MSB Integer MSB Modified Integer LSB...
Page 80: Memory Operations
Part II Software Routines Part II contains three sections: Arithmetic ......Memory Operations ....Specific Functionality .
Page 82: Clear Ram Routine
Clear RAM Microcontroller Products—Semiconductor Group Texas Instruments...
Page 84 Clear RAM This routine clears all of the internal RAM registers. It can be used at the beginning of a program to initialize the first 256 bytes of RAM to a known value. Registers A and B have the following functions in this routine: Register A holds the initialization value.
Page 86: Ram Self-Test Routine
RAM Self-Test on the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 88: Ram Self-Test Routine
RAM Self-Test This routine performs a simple alternating 0/1 test on RAM locations R3–R255 by writing an AA,55 pattern to this RAM space and then checking the RAM for this pattern. The inverted pattern is then written to RAM and rechecked. Finally, the entire RAM is cleared. If an error is found, a bit is set in the flag register. The error flag bit should be cleared before the routine is started.
Page 90: Rom Checksum On The Tms370
ROM Checksum on the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 92: Register And Function Values
ROM Checksum This routine checks the integrity of a 4K-byte ROM by performing a checksum on the entire ROM. All ROM bytes from 7002h to 7FDFh are added together in a 16-bit word. The sum is checked against the value at the beginning of the ROM (7000h, 7001h).
Page 93 Routine .TEXT 7000h ;Absolute start address FLAG .EQU R15 ;Error status CHECKSUM .EQU 12345 ;Value to be checked against .WORD CHECKSUM ;Put correct checksum into ;ROM ;Other initialization ;program here ROMCHK MOVW #7FDFh,R5 ;Starting address (end of ;memory) MOVW #0FDDh,R7 ;Number of bytes to add + 1 MOVW #0,R3 ;Reset summing register...
Page 94: Table Search With The Tms370
Table Search With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 96: Register And Expression Functions
Table Search The CMPA (Compare Register A Extended) instruction efficiently performs table searches. In the following example, a 150-byte table is searched for a match with a 6-byte string. The indexed addressing mode is used in this example and has the capability to search a 256-byte string, if needed.
Page 98: Bubble Sort With The Tms370
Bubble Sort With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 100: Register Functions
Bubble Sort This routine sorts up to 256 bytes using the bubble sort method. Longer tables can be sorted using the indirect addressing mode. Table 1. Register Functions Register Function Temporary storage register Index into the RAM Holds flag to indicate a byte swap has been made Routine .TEXT 7000h ;Absolute start address...
Page 102: Specific Functionality
Part II Software Routines Part II contains three sections: Arithmetic ......Memory Operations .
Page 104: Routine To Read A 16-Key Keyboard
Routine to Read a 16-Key Keyboard Microcontroller Products—Semiconductor Group Texas Instruments...
Page 106: Register Properties
Keyboard Scan This routine reads a 16-key keyboard through port D, returns the hex digit of the key, and debounces the key to avoid noise. A valid-key flag is set when a new key is found. Figure 1. Keyboard Scan Connections to Port D TMS370 Keys Table 1.
Page 107 Routine .TEXT 07000h FLAG .EQU ; ”Swap has been made” flag DDIR .EQU P02F ; Port D data direction register DDATA .EQU P02E ; Port D data register THESE ASSIGNMENTS NEED TO BE DONE IN THE MAIN INITIALIZATION START #00,DDATA ;...
Page 108: Dtmf Generation With The Tms370
DTMF Generation With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 110 DTMF Generator The TMS370 can be used to generate DTMF dialing. The following routine can be used to generate all 16 DTMF digits. Routine ;*************************************************************************** .TITLE ”DTMF GENERATOR” ;*************************************************************************** *** DTMF GENERATOR *** GENERATES ALL 16 DTMF DIGITS CRYSTAL: 7.158MHZ (2X COLOR BURST) OUTPUT: 4 BIT DATA TO THE LOW NIBBLE OF B–PORT UPPER NIBBLE OF B–PORT IS LEFT UNMODIFIED B0 LSB...
Page 111 CNT2 .EQU R029 ;FREQUENCY 2 COUNT ADJ2 .EQU R02A ;FREQUENCY 2 ADJUST ;R32DIGIT DURATION: 1 = 100 µS TIMER .EQU R02B BPORT .EQU P026 ;I/O PORT .EQU P027 ;DATA DIRECTION REGISTER ;*************************************************************************** ; CALCULATIONS: ; FREQ. = [(CNT,ADJ)/(# SAMPLES)] / 100.02794US ;...
Page 112 ; SINE WAVE UPDATE LOOP – 179 MACHINE CYCLES = 100 µS ; ADJ ADDED TO PREVIOUS ADJUSTMENT TO SINE TABLE ; CNT ADDED W CARRY TO PREVIOUS LSB OF 16 BIT SINE TABLE ; MSB OF 16 BIT ADDR FIXED ;...
Page 113 .WORD L1,H3 .WORD L2,H1 .WORD L2,H2 .WORD L2,H3 .WORD L3,H1 .WORD L3,H2 .WORD L3,H3 .WORD L1,H4 .WORD L2,H4 .WORD L3,H4 .WORD L4,H4 .WORD L4,H1 .WORD L4,H3 ;*************************************************************************** ; 1 COMPLETE PERIOD OF A SINE WAVE IN 64 TIME SAMPLES ; BITS ARRANGED: B0 LSB ;...
Page 114: System Integrity Check For The Tms370
System Integrity Check for the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 116 System Integrity This routine provides a simple software check of system integrity. It can be placed before the return (RTS) in a timer service routine to periodically examine the value of the return stack pointer (one byte) and return program counter value (two bytes) to see if they are within the normal operating range. Routine ;...
Page 118 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 120: Reset: Explanation Of Operation And Suggested Designs
Reset: Explanation of Operation and Suggested Designs Michael S. Stewart Microcontroller Products—Semiconductor Group Texas Instruments...
Page 122: Cold Start
Explanation of Operation and Suggested Designs The function of the RESET pin is to ensure an orderly software startup and hardware initialization. The TMS370 family of microcontrollers has three possible reset sources: 1. Low level input on the RESET pin 2.
Page 123 care must be taken in designing the reset circuitry. A typical reset circuit is illustrated in figure 1. Additional reset circuit information is available in the TMS370 Family User’s Guide. Figure 1. Typical Reset Circuit To other devices’ resets TMS370 10 kΩ...
Page 124 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 126: Spi And Sci Modules
Using the TMS370 SPI and SCI Modules Kevin L. Self Microcontroller Products—Semiconductor Group Texas Instruments Contributions by Paul Krause, Mark Palmer, and Al Lovrich...
Page 128: Introduction
Introduction The TMS370 family of 8-bit microcontrollers has been designed with two serial communications modules: the serial peripheral interface (SPI) and the serial communications interface (SCI). These two modules greatly enhance the ability of the microcontroller to interface to other serial devices and common interfaces such as the industry standard RS-232.
Page 129: Module Description: Serial Peripheral Interface (Spi)
Module Description: Serial Peripheral Interface (SPI) The SPI – How It Works The SPI module is a high-speed synchronous serial I / O port that shifts a serial bit stream of variable length and data rate between the device and other peripheral devices. The SPI is especially suited for multiprocessor and external peripheral communications where the designer needs high-speed synchronous data transfer.
Page 130: Spi Operating Modes The Master Mode
SPI Operating Modes The Master Mode The SPI operates in one of two modes. The master mode is used when the SPI controls the data transfer. The master SPI initiates and controls the data transfer by issuing the SPICLK signal. Writing data to the SPIDAT buffer starts the transfer by starting SPICLK and shifting the data out of the SPIDAT shift register onto the SPISIMO pin.
Page 131: Configuring The Spi Spi Data Format - Transmitting And Receiving
Figure 2. Master / Slave Connection SPI MASTER (MASTER/SLAVE = 1) SPI SLAVE (MASTER/SLAVE = 0) SIMO SIMO SLAVE IN/ MASTER SERIAL INPUT BUFFER SERIAL INPUT BUFFER (SPIBUF) (SPIBUF) É É É É É É É É SLAVE OUT SOMI SOMI SHIFT REGISTER SHIFT REGISTER...
Page 132: The Spiclk And Data Transfer Rate
The SPICLK and Data Transfer Rate The rate at which data is transferred out of SPIDAT is programmed by the SPI bit rate bits (SPICCR.3–5). The rate can be set from SYSCLK / 2 to SYSCLK / 256 as shown in Table 2. The SPICLK rate is only used in the master mode;...
Page 133: Controlling The Spi Through Interrupts And Flag Checking
A table showing the baud rates for common crystal frequencies versus SPI bit rate values is shown below in Table 3. The values were found using the formula SPI BAUD RATE = SYSCLK / (2 x 2 where b = bit rate specified in the SPI control register (SPICCR.5-3) (range 0–7). Table 3.
Page 134: The Talk Bit And Multiprocessor Communications
2. If the program cannot do anything until the new data value is received or transmitted, the SPI INT flag can be continuously polled until it goes high. At that time, the character can be read or a new one transmitted. It is important to use one of the above methods to wait for the data before reading or writing again.
Page 135: Data Integrity And The Spi
Data Integrity and the SPI The SPI was designed as a fast, simple interface to serial logic. As a result, it has no direct way to check for transmission errors. There are a number of software methods that can be used to check the integrity of the transmission.
Page 136: Spi Module Software Examples
SPI Module Software Examples The following are examples of the various modes of operation and common software routines used in operating the SPI. The register equate for the following examples shown below. Common Equates SPICCR .equ P030 ;SPI Configuration Control Register SPICTL .equ P031...
Page 137: Master Spi Configuration
Master SPI Configuration This routine shows how to configure the SPI to operate in the master mode. Data is sent to a peripheral device. The value needed for the SPI bit rate register is computed from the formula: SPI BAUD RATE = SYSCLK / (2 x 2 where b is the bit rate from SPICCR.3–5 in the range from 0–7.
Page 138: Slave Spi Configuration
Slave SPI Configuration This routine shows how to use the SPI interrupt to interrupt a program and load two 8-bit characters from the SPI. The program will call the SPI interrupt upon receipt of an 8-bit character, save it, and wait for one more character.
Page 139: Dynamic Bit Justification
Dynamic Bit Justification On occasion it may be necessary to transmit characters of length less than eight bits. As stated previously, the data needs to be left-justified for transmitting from SPIDAT and right-justified when read from SPIBUF. If the SPI is accessing several peripherals with different character lengths, it may be more efficient to have one subroutine justify all the transmitted data.
Page 140: Address Recognition By Spi Routine
Address Recognition by SPI In multiprocessor systems using the SPI for communication, it is necessary to keep conversations limited to two microprocessors at a time. The TALK bit is used to disable the transmit ability of a TMS370 in slave mode until it sees its address, MYADDRESS, at which time it will transmit a byte of data.
Page 141: Spi Module Specific Applications
SPI Module Specific Applications Vacuum Fluorescent Display Driver Use SPI to Transmit Data to Serial Shift Register One common and very practical use of an SPI is sending serial data to a display. The use of simple software routines can simplify your design and eliminate expensive external hardware such as decoders. This example interfaces a TMS370C010 microcontroller to a vacuum fluorescent display.
Page 142: Vacuum Florescent Interface
Figure 3. Vacuum Florescent Interface 4 DIGIT DISPLAY TMS0170 COMMON ANODE SEGMENT 1–A BIT 33 SEGMENT 1–B BIT 32 SEGMENT 1–C BIT 31 SEGMENT 1–D BIT 30 SEGMENT 1–E BIT 29 SEGMENT 1–F BIT 28 SPISIMO DATA IN SEGMENT 1–G BIT 27 SPICLK CLOCK...
Page 143 This display update routine is controlled by T1 interrupts. The compare 1 and compare 2 registers are set to control the refresh rate and intensity, respectively. Because the display is pulsed more frequently than new values are calculated, an interval counter is used to specify when it is time to update the display value. In this example, the following parameters are used: Refreshes / s = 100 (eliminates flicker in display)
Page 144 Routine The source code for this application is as follows: .title “Display Driver” This routine uses the SPI and T1 modules to output values to a serial display. The display is updated every 0.5 seconds. Display intensity is changed by toggling TlIC/CR pin. SPICCR .equ P030...
Page 145 DIGIT1 .equ ; ” DIGIT2 .equ ; ” DIGIT3 .equ ; ” TEMPMSB .equ TEMPLSB .equ DUMMY .equ Assign values for display intensity, and refresh period. TIMER .equ 3125 ;100 interrupts/sec @ 5 MHz BRIGHT .equ TIMER*9 / 10 ;Max intensity = 90 DIFF .equ BRIGHT ^(TIMER*4/ 10)
Page 146 ;T1. Enable Timer1 & SPI #005h,T1CTL3 ;Enable T1EDGE INT, enable T1C1 INT. #066h,SPICCR ;Release SPI. #0F0h,B ;Move stack pointer value to B. LDSP ;Set stack pointer. EINT ;Global interrupt enable MAIN ;Main loop Place major portion of code here. This part of the program should calculate the value to be displayed, scale it from 0 to 9999, and store the result in DISPMSB and DISPLSB.
Page 147 #060h,T1PC2 ;Reenable T1PWM. T1CCLSB,TEMPLSB ;Get current display intensity. T1CCMSB,TEMPMSB #LO(DIFF),TEMPLSB ;Toggle display intensity. #HI(DIFF),TEMPMSB TEMPMSB,T1CCMSB ;Update display intensity TEMPLSB,T1CCLSB #005h,T1CTL1 ;Restart timer. #07Fh,T1CTL3 ;Clear T1IC / CR interrupt flag. DONE ;End of display toggle: wait for ;update. TIMERINT DJNZ ICOUNT,NOTNOW ;Is it time for new value be ;displayed? ;If it is not, do not calc new value.
Page 148 characters, which gives a maximum value of 9999. #000h,DCOUNT ;Set counter for data address. NEXTCHAR DCOUNT,B ;Store DCOUNT in temp register. *DIGIT0[B],A ;Move BCD value of current char into XCHB ;Move BCD value into B. *TABLE[B],A ;Look up 7-seg value and store in A. A,SPIDAT ;Move character byte into SPIDAT ;register.
Page 149 Set up interrupt vector addresses .sect “Vectors”,07FF4h .word DISPLAY ;T1 interrupt .word START ;All other vectors go to ’START’. .word START .word START .word START .word START...
Page 150: Bootstrap Loader Reprogram Data Or Program Memory Through Spi Port
Bootstrap Loader Reprogram Data or Program Memory through SPI Port The SPI is very useful as a bootstrap loader for loading program or data information directly into RAM, EPROM, or EEPROM. The TMS370 family SPI and instruction set provide a fast, efficient way of moving serial data directly into memory.
Page 151: Dsp Controller Interface Tms370 Spi To Tms320C25 Dsp
DSP Controller Interface TMS370 SPI to TMS320C25 DSP This example shows how the SPI can be used to communicate with other microprocessors. The exact method of communication varies from system to system, but the key parts can be shown to demonstrate how to interface the TMS320C25 and TMS370 serial ports.
Page 152: Continuous Mode No Frame Synchronization Pulse
TMS320C25 wants to transmit: C25 loads DXR. ;Places data to be transmitted in buffer. C25 toggles XF low. ;Generates TMS370 INT3. TMS370 executes INT3 routine. TMS370 wants to transmit: TMS370 sets SPEAK370 bit. ;TMS370 initiates the transmission. TMS370 toggles A0 low. ;Generates TMS370 INT2.
Page 153 Different protocols have different benefits, and the protocol used depends on the requirements of the system. If the system requires continual transmission of data from the C25, then the no frame synchronization mode (no FSX / FSR pulse) allows greater throughput and less system overhead on the TMS370 processor.
Page 154 COM370 .equ ;Status register for TMS320–TMS370 comm SPEAK370 .dbit 0,COM370 ;=1 if TMS370 is transmitting FIRSTX .dbit 7,COM370 ;=1 C25 in continuous mode, need to ;generate first sync pulse DATAIN .equ ;Received data DATAOUT .equ ;Data to be transmitted .text 07000H START DINT ;Disable all interrupts.
Page 155 part to execute the INT1 service routine, which will prepare it to initiate a transfer. Since both transmissions by the TMS320 and TMS370 involve calling the TMS370 INT1 routine, the SPEAK370 bit is set by the TMS370 when it initiates a transfer. The data to be transmitted is stored in DATA OUT and received data, if it is valid, will be stored in DATA IN.
Page 156 SBIT0 SPEAK370 ;Clear TMS370 transmission flag. ;End of INT3 routine. INTR2 ;Interrupt 2 routine #01H,INT2 ;Clear and enable interrupt 2 flag. INTR1 ;Interrupt 1 routine #01H,INT1 ;Clear and enable interrupt 1 flag. Set up interrupt vector addresses. .sect “Vectors”,07FF4H .word START ;Vector goes to ’START’.
Page 157 START .equ DINT ;Disable interrupts. LDPK ;Point to page 0. FORT ;Set serial port to 8-bit mode. LALK 0ffc4h ;Enable interrupt 2. SACL STXM ;FSX is output. RFSM ;Continuos mode ;Zero the accumulator. SACL ;Initialize receiver register. SACL ;Initialize transmit register. EINT Main body of program goes here.
Page 158 SACL DATA ;Store received data. RXISR: .equ ;Serial receive interrupt EINT ;Enable interrupts. XMTISR:.equ ;Initiate data transfer to 370 routine. ;Toggle XF flag low, causes 370 ;interrupt ;and then high, to clear only, want 370 ;INT3 ;routine to execute once.
Page 159: Sci Module Description
SCI Module Description The SCI – How It Works The SCI module is a high-speed serial I / O port that permits asynchronous or isosynchronous communication between the TMS370 and other peripheral devices such as keyboards, display terminal drivers, and RS-232 interfaces. The SCI transmit and receive registers are double-buffered to prevent data collisions.
Page 160: Sci Data Frame Formats
Choosing SCI Protocols and Formats Data formatting is a characteristic of the SCI that sets it off from standard serial communications interfaces such as shift registers. The basic unit of data is called a character and is one to eight bits in length. Each character of data is formatted with a start bit, one or two stop bits, and optional parity and address bits.
Page 161: Transmitter Character Bit Length
Table 4. Transmitter Character Bit Length Character Char2 Char1 Char0 Length 3. Parity: Parity is a method of checking the integrity of a transmitted / received character. It sends an extra bit with the character to make sure that the sum of 1s in the character is an odd or even number.
Page 162: Asynchronous Communication Format
Operating Modes of the SCI The SCI has two modes of operation. The first, asynchronous, is the most commonly used mode and requires no synchronizing clock between the TMS370 and a peripheral device. When transmitting in the asynchronous mode, each bit is held for 16 shift-clock cycles. This repetition ensures that the data will be present long enough for the unsynchronized receiver to get valid data.
Page 163: Asynchronous Baud Rate Register Values For Common Sci Baud Rates
Setting the SCICLK Pins and Baud Rate The SCICLK is usually configured internally for asynchronous communications, but can be external if your application requires it. For isosynchronous communications, the clock can be configured internally or externally, depending on whether the TMS370 will be issuing the clock signal. If the SCICLK pin is not configured as the serial clock (SCICLK FUNCTION = 0), then the pin may be used for general purpose I / O by setting SCICLK DATA DIR (SCIPC1.0) to the appropriate value and reading or writing to SCICLK DATA IN or DATA OUT.
Page 164: Sci Receiver Operation
NOTE: When using an externally generated SCICLK in isosynchronous mode, the maximum speed at which the SCICLK can run is limited to SYSCLK / 10. This is necessary so that the internal clocks of the SCI have time to synchronize with the external clock. For this reason, use the TMS370 to drive the master serial clock in a system where maximum throughput is a major concern.
Page 165: Receiver Operation Flowchart
Figure 11. Receiver Operation Flowchart BEGIN SCI RECEIVER ROUTINE RXSHF – RX BUF RXRDY = 1 RXWAKE = 0 START OF FRAME? (FALLING EDGE ON SCIRXD, RXSHF – DATA LOCATION FIRST BIT = 0) RXRDY = 0 READ CHARACTER INTO RXSHF ADDRESS BIT MODE ADDRESS...
Page 166: Sci Transmitter Operation
SCI Transmitter Operation A flowchart of the operation of the SCI transmitter is shown in Figure 12. The SCI transmitter is activated by loading the transmitter buffer, TXBUF, which clears the TXRDY flag. When TXSHF, the transmitter shift register, is empty the contents of TXBUF are latched into TXSHF and the TXRDY flag is set to indicate the transmitter is ready for a new character.
Page 167: Transmitter Operation Flowchart
Figure 12. Transmitter Operation Flowchart TRANSMITTER ROUTINE IDLE MODE TXWAKE = 1 ADDRESS – TXBUF TXWAKE = 1 TXBUF – TXSHF DUMMY – TXBUF TXWAKE – WUT TXREADY = 1 TXEMPTY = 0 TXWAKE = 0 TXWAKE – WUT TXBUF – TXSHF DELAY >...
Page 168: Sci Interrupts And Flags
Data transmission is initiated by moving data into TXBUF. The status of the TXWAKE flag, set prior to writing to TXBUF, determines whether or not the current character is an address or data. The contents of TXWAKE and TXBUF are transferred to WUT (wake up temporary) and TXSHF, respectively, to be shifted out as soon as the current transmission is complete.
Page 169: Multiprocessor Communications
Multiprocessor Communications Using the SLEEP Bit Quite often several serial ports will be tied to a common line, and a method is needed to restrict the conversation between two devices to avoid a communications conflict. The SLEEP flag can be used to disable an SCI until the start of a new block, at which time an address check can be made to see if that particular receiver is being addressed.
Page 170: Using The Txwake Bit
Using the TXWAKE Bit The TXWAKE bit is used by the transmitter to format the data going out as an address frame or a data frame. If a data character is being transmitted, the TXWAKE flag is left at 0. If an address needs to be sent, TXWAKE is set to 1 before the address byte is loaded into TXBUF.
Page 171: Timing The Flow Of Data
Timing the Flow of Data Transmitting A few items need to be taken into consideration when using the SCI transmitter. It is important not to write data to the TXBUF register before it has shifted its data to the TXSHF register. This becomes more likely as the SCI baud rate decreases and it takes longer to shift out the data.
Page 172: What To Do With Transmission Errors
All of the above flags are cleared by reading RXBUF, executing an SCI SW RESET, or executing a system reset. Of course, if data integrity is not an issue, you can ignore checking for errors. Disabling parity checking decreases the number of bits sent per frame so, in effect, a faster transmission rate is achieved. In most cases, however, you will want to make sure your data has been transmitted correctly and leave parity checking enabled.
Page 173: Sci Module Software Examples
SCI Module Software Examples The following are examples of the various modes of operation and common software routines used in the implementation of the SCI. The register equates are shown below. Common Equates SCICCR .equ P050 ;SCI communication control register SCICTL .equ P051...
Page 174: Sleep Bit – Multiprocessing Control
SLEEP Bit – Multiprocessing Control By using the SLEEP bit (SCICTL2), several microprocessors can be tied to common SCIRXD and SCITXD lines. This example shows a slave microcontroller set to listen for its own address and load its RAM with a block of data of a fixed size when it is addressed. The data is received through the use of an interrupt routine.
Page 175: System Controller Configuration
System Controller Configuration In this example, the device is setup as a system controller that requests data from specific devices using the idle line protocol. The address of the device to be interrogated is stored in ADDROUT. The address is sent out and the controller waits for the data to be sent to it. If an error occurs, the controller asks for the data to be transmitted again.
Page 176: Nine-Bit Data Protocol
Nine-Bit Data Protocol Data transfer can be made more efficient by transferring more bits per character. By using the address bit mode, an extra bit of data can be added to each character, creating in effect a 9-bit character protocol. Extra bits, BITNINE for the transmitter and HIGHBIT for the receiver, are used to hold the ninth bits and can be assigned to any unused register.
Page 177: Halt Mode Wakeup Using The Sci Receiver
HALT Mode Wakeup Using the SCI Receiver In many applications, power consumption is a major concern. The TMS370 has two low power modes, HALT and STANDBY, which stop execution of various modules in the device. This greatly reduces the power used by the part. For a complete description of the powerdown/idle modes, see the TMS370 Family User’s Guide.
Page 178: Sci Module Specific Applications
SCI Module Specific Applications RS-232-C Interface Interface TMS370C050 to RS-232-C Connection The most common of the myriad of serial interfaces is the RS-232-C. Over time it has become an industry standard for digital communications, used for everything from PCs to telecommunication. This example will show the software and hardware necessary to connect a TMS370C050 to an RS-232-C interface.
Page 179: Tms370C050 - Rs 232 C Interface
SCI Module Specific Applications Figure 13. TMS370C050 – RS-232-C Interface V CC V – C1– V SS T1 OUT C2– T2 OUT R1 IN T1 IN R2 IN T2 IN SCIRXD SCICLK R1OUT R2 OUT SCITXD V CC V SS TMS370C050 MAX232 V CC...
Page 180: Routine
The framework of a program for controlling communications between the TMS370C050 and a DTE (data terminal equipment) configured device is shown below. Routine .title “RS-232-C Interface” This example shows the skeleton of a program for implementing an RS-232-C interface in hardware and software. Set up EQUATE table for peripheral file registers used in the program.
Page 181 ;Idle line protocol, 8-bit characters #HI(B9600),BAUDMSB ;Set for 9600 baud (@ 4.9152 MHz) #LO(B9600),BAUDLSB #002h,SCIPC1 ;Set SCICLK as function pin. #022h,SCIPC2 ;Set SCIRXD,SCITXD as input. #060h,SCIPRI ;SCIRX interrupt low priority #033h,SCICTL ;Release SCI, set internal clock, ;Sleep=0,RXENA,TXENA #200,B ;Start stack pointer at R200. LDSP EINT ;Enable interrupts...
Page 182 RXBUF,A ;Save received character. SCI transmitter subroutine. The subroutine waits for the other device to bring the DTR line high before transmitting. The character is then sent and the TXCTL register is polled to make sure the character has been transmitted before continuing.
Page 183: Terminal Interface Example
Dumb Terminal Driver Use TMS370C050 SCI to Interface to Dumb Terminal The power of the TMS370C050 microcontroller allows it to control a large number of tasks at the same time. The on-chip peripherals can operate independently of each other, releasing the CPU to do other tasks. This example shows a TMS370C050 microcontroller configured as a dumb terminal driver.
Page 184: Routine
Routine .title “SCI Terminal Driver” Set up equate table for peripheral registers used in program. SCCR0 .equ P010 ;System configuration register ;assignments. SCCR1 .equ P011 SCCR2 .equ P012 SCICCR .equ P050 ;SCI configuration control register SCICTL .equ P051 ;SCI operation control register BAUDMSB .equ P052...
Page 185 RXLIMIT .equ ;XOFF or XON is sent RXLIMIT2 .equ .equ 011h ;Control-Q character XOFF .equ 013h ;Control-S character .text 07000h START DINT Initialize SCI. #077h,SCICCR ;1 stop bit, even parity, asynchronous, ;Idle line protocol, 8-bit characters #000h,SCICTL ;SCI SW RESET. #000h,BAUDMSB ;Set for 9600 (@ 5 MHz) #00Fh,BAUDLSB...
Page 186 Place main block of code here. When a character is received the SCI receiver interrupt routine is called, and the character is stored in the data buffer. When the program is ready to process a character that has been received, the subroutine RXCHAR is called. When a character is ready to be transmitted, the routine TXCHAR is called, and the character is transmitted.
Page 187 GRABCHAR PUSH RXPTR,B ;Increment pointer. BTJZ #020h,B,NOROLL1 ;Does RXPTR need to be rolled over? #0,B ;Yes, reset RXPTR to start of RXBUFFER. NOROLL1 B,RXPTR ;Save new value of RXPTR. *RXBUFFER[B],A ;Get new value from RXBUFFER. SCI Transmitter Subroutine. This routine is called whenever the program is ready to transmit a character to the terminal.
Page 188 BTJZ #020h,TXPTRI,NOROLL3 ;If TXPTRI past end of buffer, clear ;it. TXPTRI ;Set TXPTRI to beginning of buffer. NOROLL3 TXDIFF ;If so, nothing to transmit. TXPTRI,B *TXBUFFER[B],A TXWAIT1 BTJZ #080h,TXCTL,TXWAIT1 ;Wait until previous characters have ;finished transmitting. A,TXBUF ;Transmit character. ;Increment TXPTR. BTJO #0FFh,TXDIFF,TXEXIT ;If no more characters to send, #0FEh,TXCTL...
Page 189 NOROLL4 B,RXPTRI ;Save new value of RXPTRI. A,*RXBUFFER[B] RXDIFF ;# of stored characters + 1. ;Restore B register contents. JBIT1 LOCSTAT,RXDONE ;XOFF already sent? Don’t send another. #RXLIMIT,RXDIFF ;Receiver buffer getting full? RXDONE ;No, exit interrupt routine. RXWAIT BTJZ #080h,TXCTL,RXWAIT ;Wait until present transmission ;complete.
Page 190 There are a few things that should be noted about any terminal controller code. The most important is to watch the timing of the transmission of X-Off and X-On characters from the receiver routines. It is important that as soon as the receiver buffer passes its limit (in this case 27 characters) that an X-Off be transmitted to make sure that the buffer does not overflow.
Page 191: Remote Data Acquisition Example
Low Power Remote Data Acquisition Use TMS370CO50 in STANDBY Mode with SCIRX Wake-Up Procedure The low-power modes and flexible serial interface of the TMS370 family make it ideal for applications involving remote sensing. In this application example, a TMS370C050 is acting as a climate recorder in a remote location.
Page 192 The program uses T1 to periodically read the A / D values and store them in ATABLE. T1 can also bring the device out of STANDBY mode through the T1 interrupt. In this way, the device will draw less than one-quarter its normal operating current most of the time.
Page 193 TXCTL .equ P054 ;Transmitter int. control/status ;register RXCTL .equ P055 ;Receiver int. control/status register RXBUF .equ P057 ;Receiver data buffer register TXBUF .equ P059 ;Transmit data buffer register SCIPC1 .equ P05D ;SCI port control register 1 SCIPC2 .equ P05E ;SCI port control register 2 SCIPRI .equ P05F...
Page 194 START DINT ;Disable interrupts while initializing. System Initialization #041h,SCCR2 ;STANDBY mode, no priv mode, no osc ;fault reset SCI Initialization #000h,SCICTL ;SCI SW RESET #077h,SCICCR ;1 stop bit, even parity, asynchronous, ;idle line protocol, 8-bit characters #000h,BAUDMSB ;Set for 9600 baud @ 5 MHz. #00Fh,BAUDLSB #001h,RXCTL ;Enable SCIRX INT.
Page 195 MAIN ;Main loop Tl Interrupt Routine When the interrupt routine is called, the part will come out of STANDBY mode. The routine will collect information from the A/D and store it in register A. The data is then loaded into ATABLE so it can be easily transmitted out.
Page 196 A,TXBUF DJNZ B,LOOP ;If not done, send next character. WAIT BTJZ #040h,TXCTL,WAIT ;Wait for last character to be sent. RXDONE ;Exit interrupt routine and go back into ;STANDBY mode. Set up interrupt vectors. .sect “VECTORS”,07FF2h .word RXINT ;SCIRX interrupt routine. .word TIMERINT ;T1 interrupt routine.
Page 197: Spi Control Registers
Appendix A: SPI Control Registers The SPI is controlled and accessed through registers in the peripheral file. These registers are listed in Table 6 and described in the TMS370 Family User’s Guide. The bits shown in shaded boxes in Table 6 are privilege mode bits;...
Page 198: Sci Control Registers
Appendix B: SCI Control Registers The SCI is controlled and accessed through registers in the peripheral file. These registers are listed in Table 7 and described in the TMS370 Family User’s Guide. The bits shown in shaded boxes in Table 7 are privilege mode bits;...
Page 199 SCI2 Designa- ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 tion SCICCR 1050h P050 STOP EVEN/ODD PARITY ADDRESS/ — BITS PARITY ENABLE IDLE WUP CHAR2 CHAR1 CHAR0 SCICTL 1051h P051 SCI SW —...
Page 200: Tms0170 Block Diagram
Appendix C: TMS0170 Specifications The TMS0170 Vacuum Fluorescent (VF) Display Driver is a one-chip interface between low voltage digital logic (5.0 V) and low voltage ( < 18 V ) VF displays. Key Features 33 individually controllable VF drivers: 8 high current drivers and 25 low current drivers Blanking input allows duty cycling of outputs for brightness control.
Page 201: Shift Register
Shift Register The 34-bit shift register consists of 34 D-type flip-flops. The bits are numbered from 33 down to 00. Each data bit is clocked in on the rising edge of the clock pin, and enters the shift register in flip-flop #33. Upon each successive clock rising edge, the bit is shifted sequentially through the shift register, from flip-flop #33 to flip-flop #00.
Page 202: Tms0170 Dip Pin Out
V SS BLANK DATA IN V DD CLOCK LOAD ENABLE LC OUTPUT-(BIT 32) DATA OUT LC OUTPUT-(BIT 21) LC OUTPUT-(BIT 20) LC OUTPUT-(BIT 22) LC OUTPUT-(BIT 25) LC OUTPUT-(BIT 23) LC OUTPUT-(BIT 24) LC OUTPUT-(BIT 30) LC OUTPUT-(BIT 19) LC OUTPUT-(BIT 13) LC OUTPUT-(BIT 12) LC OUTPUT-(BIT 14) LC OUTPUT-(BIT 17)
Page 203: Recommended Operating Conditions
Electrical Specifications Table 8. Recommended Operating Conditions Parameter Units V SS Supply Voltage V IH High Level Input Voltage V DD + 3.5 V SS + 0.3 V IL Low Level Input Voltage V DD - 0.3 V DD + 0.8 Operating Free-Air Temperature Table 9.
Page 204: Glossary
Glossary address bit mode: An SCI mode of communication incorporating an extra bit into each frame to distinguish address frames from data frames. Setting the address bit to a logic 1 signifies a frame beginning a new block. asynchronous mode: A communication format in which no synchronizing clocks are used. The data being transmitted is repeated several times and a majority vote is taken of selected bits to determine the transmitted value.
Page 205 NRZ (non return to zero) format: A communication format in which the inactive state is a logic one. RS-232-C: An industry standard serial communications interface. The most commonly used serial interface for personal computers. parity: An error checking protocol based on the assumption that the number of 1s in a character of data is odd or even.
Page 206: References
Instruments Information Publishing Center, 1984. Schwartz, Mischa. Information, Transmission, Modulation, and Noise. McGraw-Hill Book Company, 1980. T. I. Microcontroller Applications Group. TMS370 Family User’s Guide, Texas Instruments Technical Publishing. 1996. T. I. Digital Signal Processing Applications Group. TMS320C25 User’s Guide, Texas Instruments...
Page 208: Fast Method To Determine Parity
Fast Method to Determine Parity With the TMS370 Microcontroller Products — Semiconductor Group Texas Instruments...
Page 210: Register Values And Functions
Fast Method to Determine Parity This routine presents a quick way to determine the parity of a byte. Exclusive ORing all the bits of the byte together derives a single bit that is the even parity of the word. With exclusive ORing, an even number of 1s combines to form a 0, leaving either an odd 1 or 0 bit.
Page 212: Automatic Baud Rate Calculation
Automatic Baud Rate Calculation With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 214: Spi Port Interfacing
SCI Port Interfacing The SCI port provides communication with a variety of peripheral devices in either asynchronous or isosynchronous mode. The format parameters of the SCI are programmable: Table 1. Format Parameters Parameter Options Mode Asynchronous, isosynchronous Bit rate (baud) 64K possible bit rates Character length 1 to 8 bits...
Page 215: Sci Control Registers
Table 2. SCI1 Control Registers Designa- ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 tion SCICCR 1050h P050 STOP EVEN/ODD PARITY ASYNC/ ADDRESS/ BITS PARITY ENABLE ISOSYNC IDLE WUP CHAR2 CHAR1 CHAR0 SCICTL 1051h...
Page 216 BAUDLSB .EQU P053 ;Baud counter LSB TXCTL .EQU P054 ;Transmitter control RXCTL .EQU P055 ;Receiver control RXBUF .EQU P057 ;Receiver buffer TXBUF .EQU P059 ;Transmitter buffer SCIPC1 .EQU P05D ;Port control 1 (SCLK) SCIPC2 .EQU P05E ;Port control 2 (TXD,RXD) SCIPRI .EQU P05F...
Page 217: Possible Improvements
Figure 2. Autobaud Waveform Idle Start Data Data Bit 1 Bit 2 Waitstart Waitbit Setup Possible Improvements To increase flexibility and accuracy, you can improve the routine by using some of the following suggestions: For greater accuracy, time more than one bit and then divide by the number of bits. To do this, you must choose carefully the character to start the automatic baud routine.
Page 218 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 220: Using The Tms370 Timer Modules
Using the TMS370 Timer Modules Microcontroller Products—Semiconductor Group Texas Instruments...
Page 222: Introduction
Introduction The TMS370 family of 8-bit microcontrollers presently provides up to three timer modules designed to meet user demands for timer applications. This application report provides examples of software routines and hardware interface circuits designed to illustrate how the features of the timer modules may be used to solve a variety of system timer requirements.
Page 223: Module Description
Module Description Timer 1 (T1) The T1 module is available on most TMS370 devices, and contains three major blocks as shown in Figure 1: an 8-bit prescaler/clock source block, a 16-bit general-purpose timer (T1), and a 16-bit watchdog timer (WD). Additional functions of the T1 module not illustrated in Figure 1 include the interrupts and l/O pins.
Page 224: T1 Prescaler Clock Source
Prescaler / Clock Source The prescaler/clock source block provides eight available clock sources for the general-purpose timer (T1) and the WD. (See Figure 2.) These clock sources are: System clock Pulse accumulation Event input System clock with /4 prescale tap System clock with /16 prescale tap System clock with /64 prescale tap System clock with /256 prescale tap...
Page 225: T1 Counter
T1 Counter The T1 block (Figure 3) contains a 16-bit counter, a 16-bit compare register, and a 16-bit capture /compare register. It provides input capture, output compare, and external event functions. T1 can be operated in either the dual compare mode or the capture /compare mode, depending on the needs of your individual application.
Page 226: Watchdog (Wd)
Standard Watchdog (WD) The WD (Figure 4) is a separate 16-bit counter in the T1 module. The WD can be used to cause a system reset or can be software configured as a simple counter / timer, an event counter, or a pulse accumulator if the WD reset feature is not needed.
Page 227: Keyboard Scan Using T1Ic/Cr As An External Interrupt
Compare equals 2: In the dual compare mode, the capture / compare register functions as an additional compare register, and when the value of the capture / compare register matches the value of the T1 counter, the T1C2 INT FLAG bit (T1CTL3.6) is set. This action also toggles the T1PWM pin if the T1C2 OUT ENA bit (T1CTL4.5) is enabled.
Page 228: T1 I/O Pins
T1 I/O Pins The T1 module includes three I/O pins which can be dedicated for timer functions or as general-purpose I/O pins. The configuration for these pins is controlled through the timer port control registers T1PC1 and T1PC2. Their names and T1 functions are as follows: T1EVT: This pin may be used as an external clock input to the prescaler / clock source block.
Page 229: T1 Operational Modes
T1 Operational Modes The T1 module may be used in either of two modes of operation: dual compare mode or capture/compare mode. See Section 7.2 of the TMS370 Family User’s Guide for additional information. Dual compare mode: To operate in the dual compare mode, the T1 MODE bit (T1CTL4.7) must be cleared.
Page 230: Capture/Compare Mode For T1
Capture/compare mode: To operate in the capture/compare mode, the T1 mode bit (T1CTL4.7) must be set. This mode provides one compare register, and the capture/compare register is configured as a capture register. The compare register can be used to generate periodic interrupts or toggle the T1PWM pin and the capture register can be used for pulse measurement.
Page 231: T2 Interrupts
T2n (T2A and T2B) The Timer 2 (T2n) module is a 16-bit general-purpose timer available on several TMS370 devices and is illustrated in Figure 8. TMS370 devices may contain more than 1 T2n Timer Module. T2A and T2B (T2n) refer to these timer modules. T2n allows program selection of four input clock sources: system clock, external event, pulse accumulate, or no clock.
Page 232: T2 I/O Pins
Input capture 1 / external edge detection 1: When an active transition occurs on the T2nIC1 / CR pin, the T2nEDGE1 INT FLAG bit (T2nCTL2.7) is set. If the T2nEDGE1 DET bit (T2nCTL3.0) is enabled, then this action also loads the contents of the T2n counter into the capture/ compare register.
Page 233: T2 Operational Modes
T2n Operational Modes The T2n module may be used in either of two modes of operation: the dual compare mode or the dual capture mode. See Section 8.2 of the TMS370 Family User’s Guide for additional information. Dual compare mode: To operate in the dual compare mode, the T2nMODE bit (T2nCTL3.7) must be cleared.
Page 234: Dual Capture Mode For T2
Figure 10. Dual Capture Mode for T2n T2nIC.15–0 T2nCC.15 – 0 16-bit 16-bit capture/compare capture T2n PRIORITY register 1 register 2 Clock source T2nPRI.6 T2nCNTR.15–0 Level 1 Int 16-bit Level 2 Int counter T2nC1 INT FLAG Compare = T2nCTL2.5 Reset T2nCTL2.0 T2nC.15–0 T2nC1 INT ENA...
Page 235: Timer Formulas
Timer Formulas The following formulas are used to calculate the timer overflow, WD overflow, and compare register values for the T1 and T2n modules. The formulas illustrated in this section deal with time periods. Therefore, the variable SYSCLK is used in the formulas. Timer 1: T1 and WD Counter Overflow The maximum counter duration using the internal clock is determined by the internal system clock time (SYSCLK) and the prescale tap (PS).
Page 236: T1: Compare Register Formula
T1: Compare Register Formula The compare register value required for a specific timing application can be calculated using the following formula: SYSCLK x t Compare value where: t = desired timer compare period (seconds) SYSCLK = external clock frequency PS = 1, 4, 16, 64, or 256 depending on the prescale tap selected Table 3 provides some sample compare register values to achieve various desired timings using a 5-MHz SYSCLK.
Page 237: Timer 2: T2 Counter Overflow
Timer 2: T2n Counter Overflow The maximum counter duration using the internal clock is determined by the internal system clock time (SYSCLK). This relationship is shown below: Maximum counter duration (seconds) = 2 SYSCLK Counter resolution = SYSCLK where: SYSCLK = internal operational frequency Table 4 gives the real-time counter overflow rates for various SYSCLK values.
Page 238: Timer 2: Compare Register Formula
Timer 2: Compare Register Formula The compare register value required for a specific timing application can be calculated using the following formula: Compare value (SYSCLK x t) where: t = desired timer compare period (seconds) SYSCLK = internal operational frequency Table 5 provides some sample compare register values to achieve various desired timings.
Page 239: Timer Application Software Routine Examples
Timer Application Software Routine Examples The following examples show various uses of the timer modules. Each example includes source code and timing diagram. The examples shown attempt to illustrate typical timer application requirements. The Common Register Equate table for all the software examples (T2A) is shown below. (See the Conclusion section of this report to determine how to download copies of the software examples).
Page 240: Real-Time System Control: Periodic Interrupt Of T1
Real-Time System Control: Periodic Interrupt of T1 Interrupt the main program every 10 ms (100 times a second). Timer Interrupt Period 10 ms This application routine provides a T1 compare equal interrupt 100 times a second. This routine compares the present value of the 16-bit T1 counter to the value stored in the 16-bit T1C1 register. When these two registers are equal, an interrupt will occur and the T1 counter will be reset.
Page 241 10-ms Timer Interrupt Routine T1INIT MOV #0C3h,T1CM ;Value to give 10 ms with 5-MHz SYSCLK ; (C34F) MOV #04Fh,T1CL ;Must load MSB first then LSB. MOV #00000000b,T1PC1 ;T1EVT, T1PWM, AND T1IC/CR pins are set to MOV #00000000b,T1PC2 ; general-purpose input pins. MOV #00000000b,T1PRI ;Select interrupt priority level 1.
Page 242: Output Pulse Width Generation: 1-Khz Square Wave
Output Pulse Width Generation: 1-kHz Square Wave Output a 1-kHz square wave (50% duty cycle). T1PWM This application routine generates a 1-kHz square wave output signal by using the 16-bit T1 compare regis- ter to toggle the T1PWM output pin. Since the timer needs to toggle the output pin twice to produce one square wave pulse, the timer needs to toggle at a 2-kHz rate, or every 0.5 ms.
Page 243 50% Square Wave Signal Routine SQUARE MOV #009h,T1CM ;Value to give .5 ms with 5-MHz SYSCLK (9C3h) MOV #0C3h,T1CL ;Must load MSB first, then LSB. MOV #00000000b,T1PC1 ;T1EVT pin is set as a general-purpose input ; pin MOV #00100000b,T1PC2 ;Enable T1PWM pin (initial output value ;...
Page 244: Pulse Width Modulation #1
Pulse Width Modulation (PWM) #1 Output a 1-kHz signal with a fixed 20% duty cycle. T1PWM In this example of pulse width modulation, the pulse frequency remains 1 kHz while the duty cycle is 20%. The duty cycle is defined as the time the pulse remains high divided by the period of the pulse, so in this case, the pulse remains high for 0.2 ms per cycle.
Page 245 Routine MOV #013h,T1CM ;Value to give 1 ms with ; 5-MHz SYSCLK (1387h) MOV #087h,T1CL ;Must load MSB first then LSB. MOV #003h,T1CCM ;Value to give .2 ms with ; 5-MHz SYSCLK (3E7h) MOV #0E7h,T1CCL ;Must load MSB first then LSB. MOV #000000000b,T1PC1 ;T1EVT pin is set as a general- ;...
Page 246: Pulse Width Modulation #2
PWM #2 Output a 1-kHz signal with a varying duty cycle. T1PWM In this example of PWM, a fixed-frequency signal (1 kHz) is output with a varying duty cycle. The main difference between this routine and the the previous routine (PWM #1) is that the duty cycle, t , may vary.
Page 247 Routine T1INIT #013h,T1CM ;Value to give 1 ms with 5-MHz ; SYSCLK (1387h) #087h,T1CL ;Must load MSB first then LSB. HIDC,T1CCM ;Load value for the duty cycle. LODC,T1CCL ;Must load MSB first then LSB. #00000000b,T1PC1 ;T1EVT pin is set as a general- ;...
Page 248: Pulse Position Modulation (Ppm)
Pulse Position Modulation (PPM) Output a fixed 0.2-ms pulse at a variable frequency (1-kHz rate initially). T1PWM In this example of PPM, the high pulse width, t , remains constant while the periods, t , of the pulses vary. The program code for this example is similar to the PWM #2 example. In the PWM #2 example, the pro- gram changes the pulse width by varying the value in the capture/compare register.
Page 249 Routine T1INIT #013h,T1CM ;Value to give 1 ms with 5-MHz ; SYSCLK (1387h) #087h,T1CL ;Must load MSB first then LSB. #004h,T1CCM ;Load value for the .2-ms duty cycle #0E1h,T1CCL ;Must load MSB first then LSB. #00000000b,T1PC1 ;T1EVT pin is set as a general- ;...
Page 250: Pulse Width Measurement Using Pulse Accumulation Clock Source
Pulse Width Measurement Using Pulse Accumulation Clock Source Measures the positive pulse of a signal with input connected to both T1IC / CR and T1EVT pins. T1IC/CR T1EVT Time x Time y This method measures the time that a single pulse remains high. The signal line connects to both the input capture (T1IC/CR) and the event counter (T1EVT) inputs.
Page 251 Pulse Accumulation Measurement PWM Routine .REG STOREOF ;Registers used in this routine .REG STOREM .REG STOREL .REG BITS STOREOF ;Initialize the registers that will be used STOREM in this routine. STOREL BITS TIMEPULSMOV #00000010b,T1PC1 ;T1EVT and T1IC/CR pins enabled; T1PWM pin #00000010b,T1PC2 ;...
Page 252: Counting External Pulses Relative To An External Signal
Counting External Pulses Relative to an External Signal Determines the number of external clock pulses per measure signal with the measure signal attached to the T1IC / CR pin and the clock signal attached to the T1EVT pin. T1IC/CR Measure Signal Clock Signal T1EVT In this example, two signals are input to the processor, a measure signal and a clock signal.
Page 253 External Pulse Counting Routine .REG STOREOF ;Registers used in this routine .REG STOREM .REG STOREL .REG BITS STOREOF ;Clear registers used to store the sum of STOREM ; the T1EVT pulses. STOREL T1INIT #02h,T1PC1 ;T1EVT and T1IC/CR pins enabled, T1PWM pin #02h,T1PC2 ;...
Page 254: Output Pulse Drive Referenced To Input Signal: Triac Controller Or One Shot
Output Pulse Drive Referenced to Input Signal: TRIAC Controller or One Shot Output a 1-ms pulse on every positive edge of an input signal. The input signal goes to IC/CR pin. T1IC/CR T1PWM 1 ms 16-Bit Resolution Maximum In this example, a rising edge on the T1IC/CR input pin causes a 1-ms pulse to be output on the T1PWM pin.
Page 255: Pulse Width Measurement: Time Between Edges
Pulse Width Measurement: Time Between Edges Measures the time between the rising edge on one signal and the falling edge of another signal using T2A in dual capture mode. T2AIC1/CR Time Time T2AIC2/PWM How much time is between the rising edge of one signal and the falling edge of another signal? This exam- ple uses the T2A module with its dual capture registers to accurately give the answer to this problem.
Page 256 Edge Measurement Routine EDGES #02h,T2APC1 ;Set up T2AEVT pin as general-purpose input ; pin #22h,T2APC2 ;Enable T2AIC1/CR and T2AIC2/PWM pins. #8Bh,T2ACTL3 ;Select dual capture mode, enable rising ; edge of T2AIC1/CR and falling edge of ; T2AIC2/PWM to load the capture registers. #11h,T2ACTL1 ;Reset counter, enable T2A overflow ;...
Page 257: Output Pulse Generation (Delayed) Referenced To Input Signal
Output Pulse Generation (Delayed) Referenced to Input Signal Output a 1-ms pulse 5 ms after the input signal goes high. Input 5 ms T1IC/CR delay Output T1PWM 1 ms This program outputs a 1-ms pulse 5 ms after the input line goes high. This example uses T1 in the dual compare mode with the output toggle function of the T1IC/PWM pin.
Page 258 Delayed Output Pulse Generation Routine ;Put 6 ms into C1 and 5 ms into C2. ;Input pulse must remain high at least 9 ;Input = T1IC/CR output = T1PWM. DELAY #18h,T1CCM ;Value to give 5 ms with 5-MHz SYSCLK ; (1869h) #69h,T1CCL ;Must load MSB first then LSB.
Page 259: Watchdog Operation And Initialization
Watchdog (WD) Operation and Initialization A WD timer operates as a sentry to guard against improper program flow. Any time the WD is enabled to cause a system reset and then overflows without being reset by a proper value being written to the WDRST register, a system reset will occur.
Page 260 There are conditions where the program will fail to work properly due to low V levels and the WD will not catch the failure. Your system should incorporate circuitry to cause a RESET when V is out of spec. (See Figure 11.) If a reset occurs, the RESET subroutine needs to determine if the reset was caused by the WD or not by checking the WD OVRFL INT FLAG (T1CTL2.5).
Page 261: Typical Power Up/Down Circuit
Figure 11. Typical Power-Up/Down Circuit To other devices’ resets TMS370 10 kΩ Reset in 2.7 kΩ Manual 0.47 µF Reset out reset...
Page 262: Wd Reset Enable Initialization #1
WD Reset Enable Initialization #1 This example can be used for those programs that always pass periodically through two or more points (see Figure 12) in the main program routine, but not interrupt service routines. In this example, the main pro- gram resets the WD at those points by writing immediate values directly to the WD reset register.
Page 263: One Point Main Routine Plus Interrupt Operation
WD Reset Enable Initialization #2 This example can be used for those programs that have many paths through the main routine, but also con- tain a periodic interrupt service routine (ISR), as shown in Figure 13. Since a program could get lost in a continuous loop in either the main or interrupt routine, the WD routine should not be entirely contained in either one.
Page 264 Routine WDCOUNT .EQU WDSTORE .EQU ; The following routine detects whether the reset was caused by the ; WD or not. RESET BTJZ #20h,P04A,GPINIT ;Is the WD flag set? If NOT go to GPINIT. WDINIT #0DFh,P04A ;Clear the WD flag. ;Do any initialization here you desire specific to the WD.
Page 265: Wd Initialization When System Reset Is Not Desired
WD Initialization When System Reset is Not Desired If a program does not use the WD reset circuit, any erroneously enabled WD can generate a reset. If the program also clears the WD overflow interrupt flag, then the WD reset can continue to occur until a power- down.
Page 266: Specific Applications
Specific Applications This section describes sample routines for specific applications using the timer modules. Stepper Motor Control This application routine uses the T1 compare register to generate an interrupt which drives a stepper motor through the following series of activities: 1.
Page 267: Stepper Motor Drive Application Schematic
Figure 14. Stepper Motor Drive Application Schematic +5 V V CC V CC V SS (10 –20 V) V CC RESET (10 –20 V) V CC B’ (10 –20 V) XTAL2 XTAL1 V CC A’ A’ (10 –20 V) V CC B’...
Page 268: Stepper Motor Control Application Flowchart
The flowchart for the stepper motor application is shown in Figure 15. Figure 15. Stepper Motor Control Application Flowchart Begin Stepper Motor Begin T1 Application. Interrupt Routine. Initialize: 1. Stack Pointer Optional: Did T1EDGE Flag 2. Port A Cause Interrupt Do Interrupt Code Here.
Page 269 Stepper Motor Routine .title “Stepper Motor Control” Allocate register space for the four registers used in the routine. MSCOMP .equ ;Working registers for new values for LSCOMP .equ ; the T1 compare register. FLAG .equ ;Register tellS if acceleration or ;...
Page 270 Initialize the T1 module. INTPGM MOV #080h,T1CM ;Value to give minimum speed (rpm) using a MOV #00h,T1CL ; 20-MHz crystal. Must load the MS byte ; first then the LS byte. MOV #00000000b,T1PC1 ;T1EVT, T1PWM, AND T1IC/CR pins are set to MOV #00000000b,T1PC2 ;...
Page 271 T1 interrupt service routine: Routine will first check to see which of three possible flags caused the interrupt, and jump to the correct routine. If the T1C1 flag (compare register 1) is set, the STPMTR routine is entered. This routine loads the motor pole drivers with a value that causes the motor to accelerate or decelerate in either the forward or reverse direction, depending on the values of the ACCEL/DECEL and DIRECTION bits in the FLAG...
Page 272 .word START All other interrupt vectors point to .word START the reset vector. .word START .word START .word START .end...
Page 273 Time-of-Day Clock Application Routine This application routine uses the T1 compare register to generate an interrupt service routine every 1 / 10 second (100 ms), which will be used to update a time-of-day clock. The value required by the compare register to generate a 100-ms interrupt period with a 5-MHz SYSCLK is 07A11h .
Page 274: Flowchart For Time Of Day Clock Application
Figure 16. Flowchart for Time-of-Day Clock Application Main Loop T1 Interrupt Routine Begin Enter T1 Interrupt Routine. Clear and Reenable Initialize Stack the T1C1 Flag. Pointer to Begin at Increment the TENTH R10. Register. Set Up the 5 Registers Used in the Does Time = 1 s Routine.
Page 275 Time-of-Day Routine .title “Time-of-Day Clock” This routine will use T1 in the dual compare mode to implement a real-time 12-hour clock (with AM/PM flag) down to tenths of seconds. Allocate register space for the five registers used in the application routine. AMPM .equ ;AM/PM flag register...
Page 276 Initialize the clock registers to 12:00 a.m. ;Initialize SEC register to 00. ;Initialize MIN register to 00. #12h,HOUR ;Initialize HOUR register to 12. #00,AMPM ;Initialize AMPM. 0 = AM, 1 = PM #0Ah,TENTH ;Initialize TENTH register with 10. #00,T1PRI ;Set T1 priority for level 1. #7Ah,T1CM ;Move 07A11h into the T1C1 register #11h,T1CL...
Page 277: Optional Calendar Functions For The Time Of Day (Tod) Clock
Optional Calendar Functions for the Time-of-Day (TOD) Clock This code could be substituted for the T1 interrupt service routine of the previous example to give a TOD clock which keeps track of days, months, and years including leap years. To implement these functions, you need to replace the register equates, the T1 interrupt service routine, and the value of the stack pointer.
Page 278 RESTOREB POP ;Restore B with time unit ; count. DONE ;Increment the present time ; unit. A,*TIME[B] ;Restore B and A then exit. ;Return from interrupt. DOMONTH PUSH ;M O N T H S MONTH,B ;Get the value of the MONTH ;...
Page 279: Frequency Counter Application
Frequency Counter Application This routine uses the T1 module in a frequency counter application. The frequency is calculated by keeping track of the number of pulses for one second. The pulse count is input on the T1IC/CR pin, and the T1 compare register is set up to give a one-second interrupt.
Page 280 Frequency Counter Routine .title “Frequency Counter”;accurate to approx 60 kHz Allocate space for the seven registers used in the routine. COUNTH .equ ;The COUNTX registers are used to keep COUNTM .equ ; track of the external pulses on the COUNTL .equ ;...
Page 281 Begin your main program here. A simple jump/loop routine is used in this application. MAIN MAIN ;Loop on self while waiting for interrupt. T1 interrupt service routine: Routine first checks to see which of the two enabled T1 interrupt sources caused the interrupt. If the T1C1 flag (compare register 1) is set, the service routine jumps to SAVE and loads the contents of the COUNTX registers into the STOREX registers,...
Page 282: Display Dimming Application Routine
Display Dimming Application Routine Output a PWM signal with a varying duty cycle to control the brightness of a display. (VF, LED, etc.) The schematic for this application is as follows: Figure 17. Display Dimming Application Display T1PWM TMS370 Microcontroller I/O Pin ENABLE SPICLK...
Page 283 The main program loads any new values for the PWM duty cycle into the MS/LSDATA working registers. These values are checked against the latest values in the HI / LODUTY registers. If they are different, the HI / LODUTY registers are updated, and the MAIN loop compares to see if the new value is 0% or 100%. If so, the PWM pin is set either LO or HIGH.
Page 284: Display Dimming Flowchart
Figure 19. Display Dimming Flowchart Display Dimming T1 Interrupt Applications Service Routine Begin T1 INT, Begin Service Routine. Clear T1C Flag, Stop T1. Initialize: Load Upgrade Duty Cycle 1. Stack Pointer Information. 2. Registers 3. T1 Module Reset T1. Reset T1PWM Pin. Restart T1.
Page 285 Display Dimming Routine .title “Display Dimming Function” .text 7000h Allocate register space for the five registers used in the application routine. HIDUTY .equ ;Register used to store MSB of any new ; duty cycle value. LODUTY .equ ;Register used to store LSB of any new duty cycle value.
Page 286 Initialize the T1 module T1INIT #04Eh,T1CM ;Set up the T1 compare register to contain #020h,T1CL ; (4E20h). PWM frequency = 250 Hz. (The ; actual frequency is not very important ; But should be > 100 Hz.) ; Must load MSB first then LSB. HIDUTY,T1CCM ;Load value for the duty cycle.
Page 287 Continue on with the main loop. ONWARD ;(NEXT INSTRUCTION) JBIT1 NEWVALUE,CHK0 ;Check to see if a new value has been ; stored into the HI/LODUTY regs. ; If so check for 0% or 100%. ONWARD1 ; If not, branch to ONWARD1. Check to see if the NEW duty cycle is either 0% or 100%.
Page 288 The T1 interrupt service routine follows. This routine is only entered if a different duty cycle value is detected, and that new duty cycle value is: 0 < value < 4E20h. (Between 0% and 100%.) T1INT #00000011b,T1CTL1 ;Stop T1 since an update has been read. HIDUTY,T1CCM ;Load new value for the PWM duty cycle.
Page 289: Speedometer And Tachometer Display Application
Speedometer and Tachometer Display Application The purpose of this application example is to show you how a TMS370 device could be used to control a digital instrumentation cluster. The TMS370 module requirements for this example include T1, T2n, one A/D channel, and the SPI module. Also, the on-chip EEPROM could be used to keep a nonvolatile record of the odometer readings.
Page 290 Application Overview and Theory of Operation The basic functions of this application example include input signal measurement, display dimming, serial communication, and conversion of one A/D channel. The speed and tach readings are measured using the two input capture registers of T2n. The dimming of the display is controlled by reading an A/D channel which is connected to a potentiometer.
Page 291: Instrumentation Flowchart
Figure 21. Instrumentation Flowchart Begin T1 Interrupt Begin A/D Interrupt Begin Service Routine. Service Routine. Set the DELAY1 FLAG Read New Dimming Initialize Every 10th Interrupt. 1. Registers Potentiometer Value. Restart A/D for Next Read. 2. Peripheral Files 3. Stack Pointer Has a New Return From Interrupt.
Page 292 T1 Module Operation The T1 module is used to output a PWM signal to control the brightness of the display. T1 operates in the dual compare mode. The period of the PWM signal is controlled by the T1 compare 1 register, and the pulse width is controlled by the T1 capture / compare register.
Page 293: Digital Instrumentation Cluster Software Example
ADC1 Module Operation One channel of the ADC1 module (AN0) is read continually to determine the desired brightness of the display. The display brightness is application specific, so you need to define the algorithm used to determine the duty cycle of the T1 PWM signal. Also, the brightness of the display may not be in direct proportion to the duty cycle of the PWM signal.
Page 294 DATA .equ ;Set aside a 20-byte block of RAM that will be used ; to store the SPI information. ; In this example the DATA block is set up as ; follows: ; DATA : Tach information (n) ; DATA+1 : Tach information (n+1) ;...
Page 295 Set up Equate table for peripheral file registers which are used by the T1, T2n, SPI, and A/D modules. T1CNTRM .EQU P040 ;T1 counter MSB T1CNTRL .EQU P041 ;T1 counter LSB T1CM .EQU P042 ;T1 compare register MSB T1CL .EQU P043 ;T1 compare register LSB T1CCM .EQU P044...
Page 296 Begin initialization: Set up stack pointer to begin at R60. Initialize registers to their START values. Initialize the T1 module. Initialize the T2A module. Initialize the SPI module. Initialize the A/D module. START #60,B ;Initialize the stack pointer to start at LDSP register R60.
Page 297 T2AINIT #0,T2APC1 ;T2nEVT pin is set as a general-purpose ; input #00100010b,T2APC2 ;Enable T2nIC1 and T2nIC2 pin to function ; as input capture triggers. #O,T2APRI ;Set the T2n interrupt priority to level 1. #10000011b,T2ACTL3;Select dual capture mode, enable high to ;...
Page 298 Update the display. When the ignition switch is on, the display needs to be updated. How often the display needs updating depends on your system requirements. Also, all information may not need updating each time (for example, the odometer does not need updating as often as the tachometer does.) Also, the number of data bytes sent via the SPI depends on the type of display being used.
Page 299 CHKSPEED JBIT0 SPDREAD,CHKTACH ;Has a new speed value been seen by the ; T2n interrupt routine? No, jump to ; CHKTACH. SBIT0 SPDREAD ;Yes, reset the flag and calculate the ; speed variable CALCSPD ;Calculate the new speed and odometer ;...
Page 300 #01100000b,T1PC2 ;Reenable the T1PWM function with an ; initial value of 1. #01110000b,T1CTL4 ;Reenable the PWM toggling (T1C and T1CC). #00h,T1CTL1 ;Reselect the system clock as the T1 clock ; source. ;The PWM signal now runs with the new ; duty cycle until the next change. T1RET ;Return to the main routine.
Page 301 .sect ”VECTORS”,7FFCh ;Interrupt vectors: .word ADINT ; A/D vector .word T2AINT ; T2A vector .word GOBACK ; SCI TX vector (not used) .word GOBACK ; SCI RX vector (not used) .word T1INT ; Timer 1 vector .word GOBACK ; SPI vector (not used) .word GOBACK ;...
Page 302: Conclusion
Conclusion The timer modules of the TMS370 8-bit microcontroller family are designed to provide the flexibility to meet a broad range of timer and counter applications. The software and interface examples illustrate how the basic functions of the timer modules, along with other modules of the TMS370 family, can be used to provide cost-effective system solutions.
Page 303: Appendix A: Timer 1 (T1) Control Registers
Appendix A Timer 1 (T1) Control Registers T1 is controlled and accessed through registers in the peripheral file. These registers are shown in Table 7 and are described in the TMS370 Family User’s Guide. The bits shown in the shaded boxes in Table 7 are privilege mode bits;...
Page 304: Timer 1 Module Register Memory Map
Table 7. Timer 1 Module Register Memory Map Designa- ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 tion T1CNTR 1040h P040 Bit 15 T1 Counter MSbyte Bit 8 T1CNTR 1041h P041 Bit 7 T1 Counter LSbyte Bit 0...
Page 305: Timer 1 - Capture/Compare Mode
Figure 23. Timer 1 – Capture / Compare Mode 16-Bit T1C1 OUT Capture/ Prescaler/ Compare Register Clock Source T1PWM 4C.6 16-Bit Counter Reset T1C1 INT FLAG 4B.0 Level 1 INT 4F.6 Compare = Flag Level 2 INT 4B.5 T1EDGE INT ENA 16-Bit Compare T1C1...
Page 306: Appendix B: Timer 2 (T2) Control Registers
Appendix B Timer 2 (T2A) Control Registers T2A is controlled and accessed through registers in the peripheral file. These registers are shown in Table 8 and are described in the TMS370 Family User’s Guide. The bits shown in the shaded boxes in Table 8 are privilege mode bits;...
Page 307: Timer 2A Module Register Memory Map
Table 8. Timer 2A Module Register Memory Map Designa- ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 tion T2A/T2B T2A/T2B T2nCNTR 1060h/1080h P060/P080 Bit 15 T2n Counter MSbyte Bit 8 T2nCNTR 1061h/1081h P061/P081 Bit 7...
Page 308: Timer 2 - Dual Capture Mode
Figure 24. Dual Compare Mode for T2n T2nCC.15-0 16-bit capture/compare register Output Clock T2nC2 INT FLAG enable source T2nCTL2.6 T2nCTL3.5 Compare= T2nCTL2.1 T2nCNTR.15-0 T2nC2 INT ENA T2nC2 OUT ENA 16-Bit T2nPC2.7-4 counter T2nC1 INT FLAG T2nCTL3.6 T2nCTL2.5 T2nIC2/PWM Reset Compare= T2nCTL2.0 T2nC1 OUT ENA T2nC.15-0...
Page 309: Timer 2 - Dual Compare Mode
Figure 25. Dual Capture Mode for T2n T2nIC.15–0 T2nCC.15 – 0 16-bit 16-bit capture/compare capture T2n PRIORITY register 1 register 2 Clock source T2nPRI.6 T2nCNTR.15–0 Level 1 Int 16-bit Level 2 Int counter T2nC1 INT FLAG Compare = T2nCTL2.5 Reset T2nCTL2.0 T2nC.15–0 T2nC1 INT ENA...
Page 310: References
References Linear and Interface Circuits Applications, SLYA003, Texas Instruments Incorporated, 1987. TMS370 Family User’s Guide, SPNU127, Texas Instruments Incorporated, 1996.
Page 311: Glossary
Glossary capture register: A T1 or T2n register that is loaded with the 16-bit counter value when an external input transition occurs. Either edge of the external input can be configured to trigger the capture. CLKIN: The external oscillator frequency (20 MHz maximum) compare register: The compare register, in the T1 or T2n module, contains a value that is compared to the counter value.
Page 312 SPI module: Serial peripheral interface module; used to send serial data in a simple bit format to devices such as shift registers. SYSCLK: The internal system clock period. Watchdog timer: A free-running counter in the T1 module which must be cleared by the program at a set interval.
Page 314: Using Input Capture Pins As External Interrupts
Using Input Capture Pins as External Interrupts Michael S. Stewart Microcontroller Products — Semiconductor Group Texas Instruments...
Page 316: Introduction
Introduction The TMS370 family of microcontrollers are typically available with three external interrupt pins. INT1: Maskable or non maskable interrupt of general purpose input only pin INT2: Maskable interrupt or general purpose bidirectional I/O pin INT3: Maskable interrupt or general purpose bidirectional I/O pin For applications that require more than three individual external interrupts, the timer input capture pins can be used to cause interrupts.
Page 317: Timer 2B
3. Enable the selected edge to set the T2AEDGE2 INT flag by setting the T2AEDGE2 DETECT (T2ACTL4.1) bit. 4. Enable the active T2AEDGE2 INT flag to request an interrupt by setting the T2AEDGE2 INT ENA (T2ACTL3.1) bit. Timer 2B (T2B) The T2B pins T2BIC1/CR and T2BIC2/PWM may be configured to operate as external interrupts.
Page 318: Watchdog Design Considerations And Mask Options
Watchdog Design Considerations and Mask Options Michael S. Stewart Microcontroller Products — Semiconductor Group Texas Instruments...
Page 320: Introduction
Introduction Many applications require the presence of a watchdog (WD) timer to increase system integrity. The TMS370 family of microcontrollers provides three different mask options for WD timer functionality. 1. A standard watchdog for ROM-less, EPROM, and mask-ROM devices. 2. A hard watchdog for mask-ROM devices 3.
Page 321: Simple Counter
on reset and cannot be disabled. The hard WD design provides a WD counter that will always cause a system reset if the WDRST key register is not properly written. It may be used as a WD counter with variable timeout ranges based on one of four prescale clock options and the tap select. The hard WD timer is designed as part of the T1 module, and consists of the following functional blocks: 16–bit, WD which provides up to 224 clock cycles between counter resets.
Page 322 A programmable overflow interrupt. The simple counter option is available only on mask ROM devices by selecting the simple counter mask option box in the device NCRF. See the TMS370 Family User’s Guide for additional WD operational information. The limited design of the TMS370 simple counter allows the counter to be used as an counter overflow interrupt.
Page 324: T1Pwm Set-Up Routines
T1PWM Set-Up Routines Microcontroller Products—Semiconductor Group Texas Instruments...
Page 326 T1PWM Pin Set-Up This application note provides three T1PWM pin set-up routines: Routine 1 This routine starts and stops the PWM function with a certain value on the PWM pin. Starting the T1PWM pin with a specific value can be done with one instruction as shown below. The value of the data out bit will become the initial value of the PWM pin.
Page 328 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 330: Using The Tms370 Adc1 Module
Using the TMS370 ADC1 Module Henry Kwan Microcontroller Products—Semiconductor Group Texas Instruments...
Page 332: Introduction
Introduction To provide advanced performance and cost effective system solutions for complex control applications, the TMS370 family combines an 8-bit CPU containing powerful peripherals such as an Analog to Digital converters, timers, serial peripheral interface, and serial communication interface with on-chip memory: RAM, ROM, EEPROM, and EPROM.
Page 333 Figure 1. ADC1 Converter Block Diagram Port E input Port E data ENA 0 AN 0 ADENA.0 Sample Convert ADIN.0 start start ADCTL.2 – 0 ADCTL.6 ADCTL.7 Port E input Port E data AD INPUT SELECT ENA 1 AN 1 ADENA.1 ADIN.1 Port E input...
Page 334: Principles Of Operation
Principles of Operation Successive approximation is one of the most common techniques used in A / D conversion. The technique generates each bit of the digital code sequentially, starting with the MSB, and compares the analog input with binary-weighted values to produce the output in a fixed number of steps. Successive approximation provides an excellent trade-off between resolution, speed, accuracy, and cost.
Page 335: Functional Description
Functional Description The ADC1 module has ten input pins. Two pins are used for analog voltage supply: V and V . This isolates the ADC1 module from digital switching noise. The other eight pins (AN0–AN7) are used for analog input channels and can be configured as general purpose input pins if not needed. The analog reference can be either V or one of the analog input channels, AN1 to AN7.
Page 336: Analog Input Pin Connection
Figure 3. ADC1 Input Pin Model V CC D1, D2, R1, R2, TYPICAL INTERNAL EQUIVALENT PROTECTION CIRCUIT COMPONENTS 0.7 V 900 Ω SAMPLE 15 kΩ INTERCONNECTION 2 pF RESISTANCE CAPACITOR 2.7 Ω ARRAY INSIDE A / D MODULE 2 µ A 0.6 V LEAKAGE CURRENT...
Page 337 When the reference voltage, V , is at 5.1 V, one LSB corresponds to 20 mV. From the input pin model, the maximum leakage current is 2 µA (see note). That is, for the worst case of 2-µA leakage, current flow through a 1kΩ...
Page 338: Analog Input Conditioning
Analog Input Conditioning For applications dealing with stringent conditions, one might consider adding op-amps or related devices for signal conditioning, for example: buffering, amplification, level translation, linearization, or current-to-voltage conversion. The following figure and table show the op-amp symbol and some key op-amp parameters.
Page 339: Noninverting Buffer For Analog Input Pin
Figure 5. Noninverting Buffer for Analog Input Pin R3 (R1 // R2) V IN – V O = – V IN Figure 6. Inverting Buffer for Analog Input Pin LOW - PASS FILTER V IN – R3 ( R1 / / R2 ) V O = –...
Page 340: Bridge Amplifier
Figure 8. Bridge Amplifier – R ( 1 + X ) Other basic operational amplifier circuits which might be configured with the ADC1 module can provide different types of signal conditioning for different applications. For example, A unit gain voltage follower can be used as an input buffer to the ADC1 converter, A current amplifier can provide current to a voltage converter A low-pass filter can reduce system noise to achieve a better A / D conversion accuracy A logarithmic amp can compress the input signal from several orders of magnitude to a nonlinear...
Page 341: Resolution
Resolution Some applications may need more resolution than an 8-bit A / D converter can provide. One way to get around this problem is to apply scaling and offsetting in order to manipulate the input signal and use more than one channel for conversion as shown in Figure 9. Figure 9.
Page 342: Transfer Characteristics Of The Interface Circuit
op-amp) are not important. You can also use an additional op-amp or increase the gain of the amplifier to compensate for overlapping. Figure 10. Transfer Characteristics of the Interface Circuit INPUT Another technique used to increase the effective resolution is oversampling. The digital output is determined by averaging several conversion results.
Page 343: Ratiometric Conversion
high accuracy D / A converter uses the most significant six bits(with the least significant bits set to zero) to generate a precise analog signal, which is then subtracted from the input. The difference is then amplified and digitized to provide the additional least significant bits. The accuracy of the result depends on the accuracy of the generated analog signal.
Page 344: Analog Reference And Layout Considerations
Figure 13. Aliasing Signal Caused by Inadequate Sampling Rate ALIASED SIGNAL ACTUAL SIGNAL When sampling an analog signal, the Nyquist criterion must be used in order to reproduce the sampled data with no loss of information. The Nyquist criterion requires that the sampling frequency must be greater than twice that of the highest frequency to be sampled.
Page 345: Circuit With Common Impedance Earth Path
system. Filtering is added to the system only if it becomes necessary to clean up the remaining undesirable noise, especially that present in the original signal. To minimize noise and digital clock coupling to an input which might be causing conversion errors, the lead to the analog input should be kept as short as possible.
Page 346: Reference Voltage Source Impedance
Supply transients should be prevented by good decoupling practice; that is, by having a decoupling capacitor close to the V and V pins. The reference voltage (V ) can also affect the conversion accuracy. It should be kept clean, well filtered, and used only by the ADC1 converter if possible. V be from 2.5 V to V + 0.1.
Page 347: Software Routines
Software Routines The following TMS370 software routine examples show various uses of the ADC1. The register equate directives shown below are common for all examples. Common Equates ADCTL .EQU P070 ;Analog control register ADSTAT .EQU P071 ;Analog status and interrupt register ADDATA .EQU P072...
Page 348 The following section sets up the table (ATABLE) and the control registers for the ADC1. .REG ATABLE,8 ;8 BYTE TABLE THAT STORES CONVERTED DATA .REG APNTR ;POINTER TO MOST RECENTLY CONVERTED DATA .EQU P043 ;LSB TIMER COMPARE REGISTER T1CTL1 .EQU P049 ;TIMER COUNTER CONTROL REG 1 T1CTL2 .EQU...
Page 349 THE ANALOG INPUT SIGNAL IS SAMPLED AND CONVERTED CONTINUOUSLY AT A RATE OF 10 KHZ The following section is the timer interrupt routine. It sets up the time for the next conversion in the compare register and initiates the A/D conversion. The address of the label T1SERV must be placed in the interrupt vector table located at 7FF4h and 7FF5h.
Page 350: Multiple Channel Conversions
Multiple Channel Conversions The second example program samples and converts data from four channels, each of which uses a different channel for reference input. The program stores the results in a table beginning at ATABLE. The routine stops interrupting the main program after it finishes all four channels. If the main program wants more recent data, it only needs to execute the code SAMPLE, and the routine will again sample and convert all four channels of data.
Page 351 WAITC BTJO #01H,ADSTAT,WAITC ALL CONVERSIONS HAVE BEEN DONE, RESULTS ARE READY READ DATA HERE CALL SAMPLE ;SAMPLE ANOTHER SET OF DATA The following section is the subroutine to initiate the first A / D conversion. When the conversion is completed, an interrupt request will be generated. Subsequent conversions will be driven by the interrupt routine.
Page 352 ENDCON #0FEH,ADSTAT ;CLEAR THE INTERRUPT ENABLE ;TO SIGNAL THE END OF 4 CONVERSIONS EXITAD NEXTCON #09H,ADCHANL ;SET THE NEXT REFERENCE CHANNEL AND ;ANALOG INPUT CHANNEL ADCHANL,ADCTL ;SET UP INPUT AND REF CHANNEL #40H,ADCTL ;START SAMPLE DATA #0E0H,ADCTL ;START CONVERSION EXITAD ;RESTORE REGISTER INIT INTERRUPT VECTORS .SECT ”vect”,7FECH...
Page 353: Application Examples
Application Examples The following section shows some A / D conversion applications using the TMS370 family microcontrollers. All hardware is tested only under specific conditions. The user should take all standard precautions when using these circuits in their respective applications. Data Translation Many applications involve monitoring physical parameters.
Page 354 Assuming the conversion result is 01100010 (98), the value of the physical parameter can be calculated by the following equation: F(01100.010) = F(01100) + 2/8 [F(01101) – F(01100)] .REG ATABLE,33 ;33-BYTE TABLE .REG RESULT ;REGISTER FOR FINAL RESULT .REG ATPNT ;TEMPORARY REGISTER BEGIN PUSH...
Page 355 FINISH ;RESTORE REGISTERS A AND B TMS370 microcontrollers contain on-chip data EEPROM, which provides an excellent area to implement the translation table. With the on-chip EEPROM capability, the translation table can be adjusted for correction as environmental conditions change. Also, the write protection feature of the data EEPROM can be used to protect the translation table from inadvertent overwriting by the application software.
Page 356: Temperature Sensor Interface
Temperature Sensor Interface A typical temperature measurement application is shown in Figure 19. The main principle of this example applies to most other input transducers. The interfacing circuitry consists of a bridge amplifier detecting the resistance variation over the temperature range. Figure 19.
Page 357: Automatic Ranging Interface
V REF = [V = –V = –[V – V Therefore, – R ) – (V – V is a positive temperature coefficient silicon sensor approximately 0.8 % per _ C at 25 _ C. Its nominal resistance at 25 _ C is 1 k .
Page 358: Autoranging Circuit Diagram
Two output pins (INT2, INT3) are used to select the desired gain factor of the amplifier. Table 3. Amplifier Gain Factor INT2 INT3 GAIN FACTOR Figure 20. Autoranging Circuit Diagram V CC3 V CC3 30 kΩ V CC3 V IN 15 kΩ...
Page 359 Autoranging Interface Routine ANALOG INPUT CHANNEL REF CHANNEL VCC3 GENERAL PURPOSE INPUT PIN (DETERMINE GAIN RANGE) GENERAL PURPOSE INPUT PIN (DETERMINE GAIN RANGE) INT2 GENERAL PURPOSE OUTPUT PIN (SELECT GAIN RANGE) INT3 GENERAL PURPOSE OUTPUT PIN (SELECT GAIN RANGE) INT2 .EQU P018 ;INT2 PIN CONTROL REGISTER...
Page 360 #20H,A ;OPTIONAL — NOT NECESSARY IF ;ENOUGH TIME BETWEEN THE LAST INSTR ;AND THE FIRST SAMPLE INIT0 DJNZ A,INIT0 ;WAIT UNTIL OP-AMP IS STABLE #0A0H,B LDSP ;INITIALIZE STACK POINTER MOVW #0,RESULT ;INITIALIZE THE REGISTER ;INITIAL GAIN FACTOR EQUAL TO 1 EINT ;ENABLE INTERRUPT MAIN PROGRAM...
Page 361 SBIT0 SBIT1 WAIT LOWER BTJO #40H,A,CONVRT ;IS THE INPUT SIGNAL BELOW THE ;LOWER LIMIT #3,RESULT-1 ;IS THE GAIN FACTOR ALREADY SET TO ;MAX GAIN CONVRT RESULT-1 ;SET TO HIGHER GAIN FACTOR SBIT1 BTJO #1,RESULT-1,WAIT SBIT0 SBIT1 WAIT #10,A ;SET COUNT LOOP DJNZ A,LOOP...
Page 362: Interfacing A Serial A/D Converter With Tms370 Family Microcontrollers
Interfacing a Serial A/D Converter with TMS370 Family Microcontrollers The following demonstrates the interface between a 10-bit serial A / D converter (TLC1 540/1) and TMS370. This will be useful for those who want to use the TMS370 devices that do not possess on–chip ADC functions but still need A / D conversion, or those systems that require high accuracy (down to 5 mV resolution) and better isolation of the analog system from the relatively noisy digital controller.
Page 363: Interfacing Circuit Using Spi
Figure 21. Interfacing Circuit Using SPI SYSTEM CLKOUT CLOCK I / O SPICLK CLOCK TMS370 7474 7474 TLC1540 / 1 SPISIMO ADDRESS SPISOMI DATA INT3 This example program converts data from all 11 channels and stores the digital results in a table beginning at ATABLE.
Page 364 INT3 .EQU P019 ;INT3 PIN CONTROL REGISTER .REG ATABLE,22 ;16-BIT REGISTERS FOR CONVERSION RESULT .REG FLAGS ;REG FLAG TRANSL .DBIT 0,FLAGS ;INDICATE MSB OR LSB TRANSMISSION CNVCMPL .DBIT 1,FLAGS ;CONVERSIONS COMPLETE .REG ADCHANL .TEXT 7000H The following section sets up the SPI for communication. The SPI is configured as the master processor to control the communication.
Page 365 LOOP CALL RESTART ;START CONVERSIONS CHECK CNVCMPL BIT IF ALL 11 CONVERSIONS DONE WAIT BTJZ #02H,FLAGS,WAIT ALL CONVERSIONS DONE, DATA ARE READ MAIN PROGRAM GOES HERE NEED MORE RECENT DATA CALL RESTART ;START TAKING MORE DATA MORE MAIN PROGRAM The following section is the subroutine to initiate the transmission. When the transmission is completed, an interrupt request will be generated.
Page 366 SPIINT PUSH ;SAVE REGISTERS PUSH SPIBUF,A ;GET THE CONVERSION RESULT AND CLEAR ;INTERRUPT FLAG ADCHANL,B ;GET CHANNEL NUMBER NOST0 ;DO NOT DECREMENT IF THIS IS CHANNEL 0 ;GET CHANNEL NUMBER FOR RECEIVING DATA ;MULTIPLY BY 2 NOST0 BTJO #01H,FLAGS,CMPLT ;CHECK IF ALL 10 BITS DATA RECEIVED SAVE THE MSB 2 BITS’...
Page 367 TRAN2 B,SPIDAT ;INITIATE ANOTHER TRANSMISSION FLAGS ;CLEAR THE FLAG, INDICATE THE ;CHANNEL ADDRESS ALREADY TRANSMITTED, EXITSP ;RESTORE THE REGISTERS. EXIT INIT INTERRUPT VECTORS .SECT “vect”,7FECH .WORD 0,0,0,0,0,SPIINT,0,0,0,INIT...
Page 368: Using Software To Interface With A Serial A/D Converter
Using Software to Interface With a Serial A/D Converter This section demonstrates the interface of TLC1540 through software routines. This will be useful for cost sensitive applications that need to minimize external hardware. Four general purpose I / O pins are used to interface with the TLC1540. The following software example performs the same function as explained in the “Using On-Chip SPI”...
Page 369 Interfacing Software Routines D3/CLKOUT GENERAL PURPOSE OUTPUT PIN, (CONNECT TO TLC1540/1 I/O CLOCK AND TLC1540/1 SYSTEM CLOCK) INT1 GENERAL PURPOSE INPUT PIN (CONNECT TO TLC1540/1 DATA OUTPUT) INT2 GENERAL PURPOSE OUTPUT PIN (CONNECT TO TLC1540/1 ADDRESS INPUT) INT3 GENERAL PURPOSE OUTPUT PIN (CONNECT TO TLC1540/1 CHIP SELECT) DPORT1 .EQU...
Page 370 BEGIN #18H,INT3 ;SET INT3 AS OUTPUT PIN #18H,INT2 ;SET INT2 AS OUTPUT PIN #00H,DPORT1 ;SET CLKOUT AS GENERAL PURPOSE I/O #00H,DPORT2 #08H,DDIR #0A0H,B LDSP ;INITIALIZE STACK POINTER TO 0A0H #22,B AGAIN A,*ATABLE–1[B] ;INITIALIZE THE TABLE DJNZ B,AGAIN EINT ;ENABLE INTERRUPT LOOP CALL CONVRT...
Page 371 The following section is the subroutine CONVRT that initiates the A / D conversion. It sets up the channel address and invokes subroutine ADTRAN for serial transmission. When the transmission finishes, it saves the previous conversion result in ATABLE and generates 44 I / O clocks for current A / D conversion. SUBROUTINE SECTION SUBROUNTINE CONVRT ENTER : NO PARAMETERS...
Page 372 REPEAT SBIT1 IOCLK ;44 SYSTEM CLOCKS FOR CONVERSION SBIT0 IOCLK DJNZ B,REPEAT DJNZ CHNLCNT,NEXT The following section is subroutine ADTRAN that handles the communication between TMS370 and TLC1540/ 1. SUBROUTINE ADTRAN BIT BANGING ROUTINE TRANSMITTING AND RECEIVING DATA TO / FROM TLC1540 ENTER : B - AD CHANNEL ADDRESS (UPPER 4 BITS) EXIT : RESULT - 10-BIT RESULT ADTRAN...
Page 373 BIT0 SBIT0 IOCLK DJNZ BITCNT,ADRTRA FLAG ;UPDATE THE FLAG BTJZ #1,FLAG,DONE #2,BITCNT ;SET COUNTER FOR THE LAST 2 BITS SBIT1 CS ;CS GO INACTIVE AFTER THE EIGHTH ;I/O CLOCK, CS MUST BE DEACTIVATED ;TWO I/O CLOCK BEFORE THE END OF ;TRANSMISSION BIT1 DONE...
Page 374: Conclusions
Conclusions This application report provides information on using the ADC1 converter module with the TMS370 family microcontrollers to a provide cost-effective system solution. Examples have been given to demonstrate the operation of the ADC1, typical methods of interfacing to the external circuits, and interactions with other modules.
Page 375: Appendix A: A Dc1 Control Registers
Appendix A: A DC1 Control Registers The ADC1 is controlled and accessed through registers in the peripheral file. These registers are listed in Figure 23 and described in the TMS370 Family User’s Guide. The bits shown in shaded boxes in Figure 23 are privilege mode bits: they can only be written to in the privilege mode.
Page 376: A/D Transfer Characteristics
Appendix B ADC1 Errors Figure 24 shows the transfer characteristics of the A / D conversion and the related errors. Figure 24. A/ D Transfer Characteristics DIGITAL OUTPUT CODES 0...111 0...110 IDEAL A / D CHARACTERISTICS 0...101 X = THEORETICAL MIDPOINT 0...100 0...011 SPEC RANGES INDICATED...
Page 377: Functional Block Diagram Of Tl505C Interface With Tms370
Appendix C External A / D Converters The following section provides some hints for using external components to perform A / D conversion. This will be useful for low end applications using TMS370 without A/D but still needing A / D conversion, or those applications that need more resolution than the on-chip A / D can provide.
Page 378: Conversion Timing Diagram
Figure 26. Conversion Timing Diagram V O (ofs) INTEGRATOR OUTPUT COMPARATOR OUTPUT V 1 = V 2 – V 3 = V I + V O (ofs) CONTROL ANALOG SWITCHES CLOSED S1, S2 S1, S4 H = V IH , L = V IL V IN = –...
Page 379: Functional Block Diagram Using D/A Converter As A/D
Instead of using commercial A / D converters, you can also build your own A / D. One of the simplest implementations is to use a 10-bit D / A converter with a voltage comparator to determine the input voltage. The TMS370 performs a binary search to determine the digital value of the input voltage (10 conversions for 10-bit D / A converter).
Page 380: Functional Block Diagram Using V/F Converter As A / D
Another way to implement an A / D is by using a voltage / frequency (V / F) converter. The frequency output can be measured by the on-chip timer using the input capture function. The V / F converter can generate frequency outputs up to 500 kHz.
Page 381: Test Conditions
Appendix D: A /D Testing The following section provides information about testing two A / D converter parameters, absolute accuracy and differential linearity error. Table 4. Test Conditions SYSCLK 0.5 MHz and 5 MHz V CC3 5.5 V V ref 5.1 V 2 µs (SYSCLK = 5 MHz) Sampling time...
Page 382: Block Diagram Of Test Set Up
Figure 29. Block Diagram of Test Set-Up 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH –15 V 1 ....16 1 ....16 DAC-HP16BMC DAC-HP16BMC 2.2 mΩ...
Page 383: Code Width Measurement
Figure 30. Code Width Measurement 80 MIN MIN INPUT VOLTAGE FOR CODE 80 7F MIN MIN INPUT VOLTAGE FOR CODE 7F 7F MAX MAX INPUT VOLTAGE FOR CODE 7F 7E MAX MAX INPUT VOLTAGE FOR CODE 7E 1 ⁄ TO SATISFY THE 2 LSB DIFFERENTIAL NONLINEARITY ERROR 7F MAX –...
Page 384: Codes Having Maximum Differential Linearity Error
Figure 31. Codes Having Maximum Differential Linearity Error 0000 0000 0000 0011 0000 0001 0000 0100 0000 0111 0000 1111 0000 1000 0001 0000 0001 1111 0000 1111 0010 0000 0100 0000 0111 1111 1000 0000 Figure 32. Differential Linearity Error TMX37050 TEMPERATURE= 25 C, FREQUENCY = 2MHz.
Page 385: Glossary
Glossary aliasing signal: The false lower frequency signal reconstructed from an analog input because of insufficient sampling rate (see Nyquist Criterion). conversion speed: Provides an indication of system sampling rate. It is usually expressed in conversions per second. code width or step width: The voltage corresponding to the difference between two adjacent code transitions.
Page 386: References
McCreary, James L, “All-MOS Charge Redistribution Analog-to-Digital Conversion Technique.” IEEE Journal of Solid-State Circuits, 1975. Pippenger, D. E., and Tobaben, E. J. Linear and Interface Circuits Applications, Texas Instruments Technical Publishing, Dallas, Texas, 1986. Sheingold, Daniel H, Transducer Interface Handbook, Analog Devices, Inc, Massachusetts, 1981.
Page 388: Analog-To-Digital (A/D) Helpful Hints
Analog-to-Digital (A/D) Helpful Hints Michael S. Stewart Microcontroller Products — Semiconductor Group Texas Instruments...
Page 390: Power Down Operation
Analog-to-Digital V and V Pins The A/D module has been designed with separate power (V ) and ground (V ) reference pins. This was done to allow a greater level of noise immunity for the A/D conversion requirements. When using the A/D module, the V and V pins must be connected to an appropriate power source and current return...
Page 391: Example : Typical A/D Input Selection And Conversion Process
NOTE: The TMS370 devices require the SAMPLE bit be set before the CONVERSION bit. This requirement means that separate instructions are required to set these two bits. The maximum SYSCLK frequency for the TMS370 family is 5 MHz. The MOV #iop,Pd instruction format requires 10 SYSCLK cycles to complete.
Page 392 WAIT JBIT0 AD_FLAG,WAIT ;Wait on the AD INT FLAG bit to be set. ADDATA,A ;Read conversion data, store in BUFFER. A,BUFFER...
Page 394 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 396 PACT Command Macros Microcontroller Products—Semiconductor Group Texas Instruments...
Page 398: Pact Command Macros
PACT Command Macros This application note contains macro definitions for all PACT commands and definitions. All the actions desired in each of the commands/definitions must be passed in the macro as they are defined in the following equates. All the actions are passed as one parameter in the macro. These actions are concatenated by ’|’...
Page 399 least significant byte of this command STDCMP .MACRO cmpval,pin,actions,lab .var b1,b2,b3,b4 ((pin.v<1)|(pin.v>8))&((actions.v&enable)=enable) ** ERROR, pin selection is illegal ** .endif (actions.v&0FD90h)!=0 ** ERROR, illegal action specified ** .endif .asg cmpval.v&0FFh,b1.v .asg (cmpval.v>>8)&0FFh,b2.v (pin.v<1)|(pin.v>8) .asg 1,pin.v .endif .asg pin.v–1,pin.v .asg actions.v&63h|pin.v<<2,b3.v .asg actions.v&0Ch|actions.v>>8&2h,b4.v .byte b1.v,b2.v,b3.v,b4.v...
Page 400 :lab: .equ r:b1.v: .endif .ENDM ;DOUBLE EVENT COMMAND ;DEVCMP <event value 1>,<event value 2>,<output pin>,<actions>, ;<register label> ;event value 1: 8-bit value compared to the event counter ;event value 2: 8-bit value compared to the event counter ;pin: Output pin ;possible actions: nxt_def,int_evt1,set_pin,clr_pin,step,opp_act,int_evt2 rst_def_ev2,cap_def_ev1,cap_def_ev2,enable,...
Page 401 ((period.v>>8)&0FFh) > 1Fh .asg (period.v>>9)&70h|(period.v<<3)&80h|08h,b3.v (period.v&0Fh)!=0 ** ERROR, Max. Timer value truncated in last 4 bits ** .endif .else .asg (period.v<<3)&0F0h|(actions.v&0Ch)>>1,b3.v period.v&01h!=0 ** ERROR, Max. Timer value truncated in last bit ** .endif .endif tmrval.v&01h!=0 ** ERROR, Timer value truncated in last bit ** .endif .asg b3.v|actions.v&0Ch>>1,b3.v...
Page 402 ;OFSTMR <max event count>,<actions>,<inital value>,<register label> ;max event count: The maximum value the event counter may reach before ;being reset. ;possible actions: step,int_max_evt,enable,rst_def_tmr, vir_cap,def_cap,int_evt ;initial value: 16-bit initial timer value ;register label: a symbol to be equated to the register containing the least significant byte of this definition OFSTMR .MACRO maxcount,actions,tmrval,lab .var...
Page 404: Pact Module Sample Routines
PACT Module Sample Routines J. L. Pettegola Microcontroller Products—Semiconductor Group Texas Instruments...
Page 406: Introduction
Introduction This report provides software routines to illustrate the basic functions and characteristics of PACT8 module in the TMS370Cx36 8-bit microcontroller. Each example includes the source code and related timing diagrams. All routines are based on a system clock of 200 ns. For a complete description of the PACT8 module, refer to the TMS370Cx36 8-Bit Microcontroller data sheet, literature number SPNS039, or the TMS370 Family User’s Guide, literature number SPNU127.
Page 407: Using The Hardware Default Timer
Using The Hardware Default Timer Square Wave PWM On OP1 This routine shows how to generate a simple square wave on pulse width modulator (PWM) output OP1. Figure 1. Square Wave T=26.5 ms PACT Global Initialization Set the watchdog (WD) time out in the global function control register (or disable it if no watchdog is required).
Page 408: Command / Definition (Cmd/Def) Initialization
Command/Definition (CMD/DEF) Initialization CMD/DEF 1: STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 time slot or TS) COMPARE VALUE = 10000H/2 = 8000H => DUTY CYCLE 50% SET OP1 ON COMPARE = 8000H Timer Reserved Select Compare Value 8000h D31..D28 D20..D18 D15....D0 .WORD 00820H,08000H ;SET OP1 ON 08000h (DEFAULT TIMER)
Page 409 Square Wave PWM Routine .TEXT 7000H .global deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ; Command/definition area start register CDEND .EQU p042 ; Command/definition area end register PACTSCR .EQU p040 ;...
Page 410: Pwm With Period And Duty Cycle Change
PWM With Period and Duty Cycle Change Figure 2. PWM With Period and Duty Cycle Change T=65.5 ms O P 1 O P 2 O P 3 PACT Peripheral Initialization PACT RESOLUTION 1 S, PRESCALER VALUE = 05H, FAST MODE BUFFER NOT USED (MIN), NO CAPTURE =>...
Page 411 CMD/DEF 3: STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 TS) COMPARE VALUE = 04000H ; DUTY CYCLE 50% SET OP3 ON COMPARE. Timer Reserved Select Compare Value 4000h D31..D28 D20..D18 D15....D0 .WORD 00828H,04000H ;SET OP3 ON 04000h (DEFAULT TIMER) CMD/DEF 4: STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 TS) COMPARE VALUE = 0C000H ;...
Page 412 Square Wave PWM Routine With Period and Duty Cycle Change .TEXT 7000H .GLOBAL deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ; Command/definition area start register CDEND .EQU p042 ;...
Page 413: Example 1 Pwm
Virtual Timer PWM The standard way to create a PWM is to use a virtual timer definition associated with a standard compare command. The programmer can add any number of virtual timers for an application and is only limited by the number of time slots allowed for the application PACT resolution.
Page 414 CMD/DEF 3: STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 (1 TS) SET OP1 ON VIRTUAL TIMER 1 VALUE = 0000H Timer Reserved Select Compare Value 0000h D31..D28 D20..D18 D15....D0 .WORD 0820h,0000h ;SET OP1 ON 0000H VIRT1 CMD/DEF 4: STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 (1 TS) RESET OP1 ON VIRTUAL TIMER 1 VALUE = 0001H NEXT IS A TIMER DEFINITION Timer...
Page 415: Timing Diagram
Figure 4. Timing Diagram 800nS PACT RESOLUTION CMD/DEF SCAN DEFAULT TIMER VIRTUAL TIMER 1 VIRTUAL TIMER 2 NOTES: This example shows the maximum speed resolution in normal mode. By changing the timer max value you can modify the PWM period. By changing the compare values you can modify the duty cycle. It is possible to increase the speed resolution by using the step mode.
Page 416 Virtual Timer PWM Routine .TEXT 7000H .GLOBAL deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ; Command/definition area start register CDEND .EQU p042 ; Command/definition area end register PACTSCR .EQU p040 ;...
Page 417: Pwm Example 2 W Ave
Pulse Width Modulation Example 2 This example show how to combine compare commands and the virtual timer. Figure 5. PWM O P 2 T1 T1 T1 T1 = 1 s, T2 = 2 s, T3 = 4 s, T4 = 4 PACT Configuration PACT RESOLUTION = T1 = 1mS =>...
Page 418 CMD/DEF 3: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) SET OP2 ON COMPARE VALUE = 0001H Timer Reserved Select Compare Value 0001h D31..D28 D20..D18 D15....D0 .WORD 00824H,0001H ;SET OP2; FIRST OP2 RISING EDGE,ON COMPARE VALUE = 0001H CMD/DEF 4: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) SET OP1 ON COMPARE VALUE = 0002H Timer Reserved...
Page 419 CMD/DEF 8: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) SET OP2 ON COMPARE VALUE = 0007H Timer Reserved Select Compare Value 0007h D31..D28 D20..D18 D15....D0 .WORD 00824H,0007H;SET OP2; SECOND OP2 RISING EDGE, ON COMPARE VALUE = 0007H CMD/DEF 9: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) RESET OP2 ON COMPARE VALUE = 0009H Timer Reserved...
Page 420: P Act Timing Diagram
Figure 6. PACT Timing Diagram PACT RESOLUTION CMD/DEF SCAN DEFAULT TIMER VIRTUAL TIMER...
Page 421 Pulse Width Modulation Routine #2 .TEXT 7000H .global deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ; Command/definition area start register CDEND .EQU p042 ; Command/definition area end register PACTSCR .EQU p040 ;...
Page 422: External Event, Event Delay, And Sync Pulses
.WORD 00820H,0006H ;SET OP1; SECOND OP1 RISING EDGE, ON COMPARE ;VALUE = 0006H .WORD 00804H,0005H ;RESET OP2; FIRST OP2 FALLING EDGE, ON COMPARE ;VALUE = 0005H .WORD 00800H,0004H ;RESET OP1; FIRST OP1 FALLING EDGE, ON COMPARE ;VALUE = 0004H .WORD 00820H,0002H ;SET OP1;...
Page 423 BUFFER NOT USED (MIN), NO CAPTURE => MODE A => START ADDRESS = 01EFh 6 CMD/DEF => END ADDRESS = START ADDRESS - (4 x NB CMD/DEF) + 1 = 01D8h MAX EVENT COUNTER VALUE = DON’T CARE (01h for example) SET OP1 ON 0001h,RESET ON 0002h OF OFFSET TIMER SET OP2 ON 0002h,RESET ON ZERO OF VIRTUAL TIMER CONNECT OP2 TO CP6 TO GENERATE EXTERNAL EVENT...
Page 424 CMD/DEF 4: OFFSET TIMER DEFINITION (2 TS) MAX EVENT COUNTER VALUE = 00H (DON’T CARE) ENABLE TIMER, NO CAPTURE, NO INTERRUPT. Maximum Event Virtual Timer Offset Counter Value Value 0000h D31......D24 D15......D1 .WORD 00004H,0001H ;MAX EVENT COUNTER VALUE = 0000h, NO INTERRUPT, NO ;CAPTURE.
Page 425: P Act Timing Diagram
CMD/DEF 5: STANDARD COMPARE COMMAND ON OFFSET TIMER (1 TS) SET OP1 ON COMPARE VALUE = 0001H Timer Reserved Select Compare Value 0001h D31..D28 D20..D18 D15....D0 .WORD 00820H,0001H ;SET OP1 ON COMPARE VALUE = 0001h CMD/DEF 6: STANDARD COMPARE COMMAND ON OFFSET TIMER (1 TS) RESET OP1 ON COMPARE VALUE = 0002H Timer Reserved...
Page 426 Routine ;It is necessary to connect OP2 and CP6 together to perform this application. .text 7000h .global deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ; Command/definition area start register CPCTL3 .EQU P04C ;...
Page 427: External Event And Pwm
PWM Generation On Selected Event This example shows how conditional compare commands and event compare commands can generate a pwm on selected event. Figure 9. External Event and PWM E n + 4 E n + 5 E n + 1 E n + 2 E n + 3 E X T E V E N T...
Page 428 CMD/DEF 2: VIRTUAL TIMER DEFINITION (2 TS) MAX VALUE = 0008H Maximum Virtual Timer Value “0” Virtual Timer value “0” “0” 0000 “0” D31........D23 D22...D20 D15........D1 .WORD 00044H,0000h ;MAX VALUE = 0008h, D19 = 0 CMD/DEF 3: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) SET OP2 ON COMPARE VALUE = 0001H,RESET ON ZERO NEXT IS A TIMER DEFINITION Timer...
Page 429 CMD/DEF 7: CONDITIONAL COMPARE COMMAND ON OFFSET TIMER (1 TS) EVENT COMPARE VALUE = 01h SET OP1 ON COMPARE VALUE = 0005H SAME ACTION ON NEXT EVENT IF NECESSARY Event Compare Value Pin Select Timer Compare Value 0005h D31......D24 D20..D18 D15..........D0 .WORD 001E0H,0005H ;SET OP1 ON EVT CMP = 01h, TIMER CMP = 0009h, SAME ACTION...
Page 430: P Act Timing Diagrams
Figure 10. PACT Timing Diagrams Action On Event N+1 PACT RESOLUTION CMD/DEF SCAN EXT EVENT ON CP6 INTERNAL EVT SYNC EVENT COUNTER OFFSET TIMER 2m s 1 m s 4m s Action On Event N+3, N+4, N+5 1 m s PACT RESOLUTI ON CMD/DEF SCA N EXT EVENT ON CP6...
Page 431 PWM Generation on Selected Event Routine ;It is necessary to connect OP2 and CP6 together to perform this application. .TEXT 7000H .GLOBAL deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ;...
Page 432: Cp1 And Cp2 Events
.WORD 001E0H,0005H ;SET OP1 ON EVT CMP=01h,TIMER CMP=0009h,SAME ;ACTION ACTION .WORD 00180H,0003H ;RST OP1 ON EVT CMP=01h,TIMER CMP=0003h .WORD 001A0H,0002H ;SET OP1 ON EVT CMP=01h,TIMER CMP=0002h .WORD 00504H,0001H ;OFFSET TIMER DEFINITION, MAX EVENT VALUE = 05H ; = 05 .WORD 00A25H,0002h ;SET OP2 ON VALUE 0002H,RST ON ZERO,NEXT IS A DEF .WORD...
Page 433 PACT Command / Definition Initialization CMD/DEF 1: DUMMY STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 TS) USE ONLY TO IDENTIFY NEXT ENTRY AS A TIMER DEFINITION NO ACTION Timer Reserved Select Compare Value 0000h D31..D28 D20..D18 D15....D0 .WORD 00001H,0000h ;NEXT IS A TIMER DEFINITION CMD/DEF 2: VIRTUAL TIMER DEFINITION (2 TS) MAX VALUE = 1000H Maximum Virtual Timer Value...
Page 434 INIT PACT PERIPHERAL FRAME ;********************************************************** #003H,PACTPRI ;DISABLE WATCHDOG, MODE A #010H,B LDSP #000H,CPPRE ;INPUT CAPTURE PRESCALER DIVIDE ;BY 1 #(STARTAD-0100H-080H),CDSTART ;START AD, CMD/DEF INT DIS #(ENDAD-0100H),CDEND ;END AD #013H,PACTSCR ;SYSCLK DIVIDED BY 4 => ;RESOL=800uS AT 20MHZ ;********************************************************** MAIN PGM ;********************************************************** MAIN #020H,PACTSCR...
Page 435 R0FA,R0F6 R0F9,R0F5 ; RESULT STORED IN REGISTERS R0E5, R0E6, R0E7 R0F7,R0E7 R0F6,R0E6 R0F5,R0E5 ;RETURN TO MAIN PGM ;********************************************************** CP2 INTERRUPT VECTORS ;********************************************************** .sect “VECT”,07FBAH ;PACT INTERRUPT VECTOR .WORD ITCP2 ;CP2 IT VECTOR ;********************************************************** INIT PACT CMD/DEF AREA ;********************************************************** .sect “CMDEF”,(ENDAD) ;CMD/DEF SECTION PROGRAM .WORD 0A00h,0010h...
Page 436: Cp6 Pwm
Using The Circular Buffer Registers The circular buffer is used to capture CP3, CP4, CP5, or CP6. It is very useful in case of fast event occurrences when the CPU does not enough time to treat all events and discharges them from data storage manipulation.
Page 437 CMD/DEF 2: VIRTUAL TIMER DEFINITION (2 TS) MAX VALUE = 0008H Maximum Virtual Timer Value Virtual Timer value “0” 0000 “0” D31........D23 D22...D20 D15........D1 .WORD 00044H,0000H ;MAX VALUE = 0008h, D19 = 0 CMD/DEF 3: STANDARD COMPARE COMMAND ON VIRTUAL TIMER (1 TS) Timer Reserved Select...
Page 438 Using the Circular Buffer Registers Routine ;It is necessary to connect OP1 and CP6 together to perform this application. .TEXT 7000H .global deb ;********************************************************** STARTAD .EQU 01E3H ;size buffer = 4 registers PACTPRI .EQU p04F ; Global function control register CDSTART .EQU p041 ;...
Page 439 ;********************************************************** ITBUFF MOV #000H,CPCTL3 ;DISABLE BUFFER CAPTURE AND CLEAR ITBUFF FLAG AND #0BFH,CPPRE ;CLEAR ITBUF FLAG MOV BUFPTR,A ;TEST IF BUFFER FULL CMP #0F2H,A JZ BFULL BHALF #0F3H,B ;B = STORAGE POINTER CALL STORE ;CP6 PERIOD MEASUREMENT R0F3,R0EF R0F2,R0EE R0F1,R0ED ;RESULT STORED IN REGISTER R0ED, R0EE, R0EF ;RETURN TO MAIN PGM BFULL...
Page 440 CMP R090,B LOOP ;********************************************************** BUFFER INTERRUPT VECTOR ;********************************************************** .sect “VECTBUFF”,07FB0H ;BUFFER INTERRUPT VECTOR .WORD ITBUFF ;BUFF IT VECTOR ;********************************************************** INIT PACT CMD/DEF AREA ;********************************************************** .sect “CMDEF”,(ENDAD) ;CMD/DEF SECTION PROGRAM .WORD 0A00h,0001h ;RST OP1 ON 0001H VIRT1,SET ON ZERO .WORD 0044h,0000h ;VIRT1 MAX VALUE = 0008H .WORD 0001h,0000h...
Page 441: Step Mode Pwm
Using PACT Step Mode The step mode is useful for applications that require more time slots than normally allowed for a specific resolution. To illustrate, look at the square wave PWM. This example is done with a resolution of 1 s for 20MHz.
Page 442 PACT Command / Definition Initialization CMD/DEF 1: DUMMY STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 TS) USE ONLY TO ENABLE STEP MODE, NO ACTION Timer Reserved Select Compare Value 0000h D31..D28 D20..D18 D15....D0 .WORD 0040h,0000h ;STEP ENABLE CMD/DEF 2:DUMMY STANDARD COMPARE COMMAND ON DEFAULT TIMER (1 TS) USE ONLY TO IDENTIFY NEXT COMMAND AS A TIMER DEFINITION Timer Reserved...
Page 443: P Act Timing Diagram
CMD/DEF 6: STANDARD COMPARE COMMAND ON VIRTUAL TIMER 2 (1 TS) RESET OP1 ON VIRTUAL TIMER 2 VALUE = 0001H INVERTED ACTION (SET OP1) ON ZERO VIRT2 Timer Reserved Select Compare Value 0001h D31..D28 D20..D18 D15....D0 .WORD 0A00h,0001h ;RESET OP1 ON 0001H VIRT2,INV ACTION ON ZERO VIRT2 CMD/DEF 7: STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 (1 TS) SET OP2 ON VIRTUAL TIMER 1 VALUE = 0001H Timer...
Page 444 Using the PACT Step Node Routine ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU P04F ; Global function control register CDSTART .EQU P041 ; Command/definition area start register CDEND .EQU P042 ; Command/definition area end register CPCTL3 .EQU P04C ;...
Page 445: Programming The Pact Sci
Programming The PACT SCI Programming the PACT SCI is very simple. First, define a special SCI timer definition in the CMD/DEF area in order to set the appropriate baud rate for receive and/or transmit mode. In this example, we are using the same baud rate for receive and transmit.
Page 446 Programming the PACT SCI Routine ;It is necessary to connect TXD and RXD together to perform this application. .TEXT 7000H .global deb ;********************************************************** START END ADDRESS DEFINITION ;********************************************************** STARTAD .EQU 01EFH PACTPRI .EQU P04F ; Global function control register CDSTART .EQU P041 ;...
Page 447 ;LOOP MAIN PGM ;********************************************************** INTERRUPT SCI TRANSIT ;********************************************************** ITTXD MOV #055H,TXBUFP ;LOAD DATA TRANSMIT = 055H IN TRANSMIT BUFFER ;********************************************************** INTERRUPT SCI RECEIVE ;********************************************************** ITRXD MOV RXBUFP,A ;READ SCI RECEIVE BUFFER #055H,A ;TEST IF RECEPTION OK JNZ ERROR ERROR DINT ;DISABLE INT TO STOP TRANSMISSION IN CASE OF ERROR.
Page 448: P Act Timing Diagram
Appendix Figure 15. PACT Timing Diagram Scan Resolution Time Slot CPU System Clock PACT Prescaled Clock Time Base (default timer) Start Scan Commands Reads Internal Actions PACT Output Pins Actions Actions from those commands w ithin 1 to N Action s from those with EVEN compare values commands w ithin 1 to N with ODD compare values...
Page 449: Organization Of The Capture Registers And The
PACT Input Capture Structure Figure 17. Organization of the Capture Registers and the Circular Buffer in Dual Port RAM Dedicated Capture Register 1 Dedicated Capture Register 2 Dedicated Capture Register 3 Mode Dedicated Capture Register 4 Circular Buffer (32 Bit Captures) Event Only 8 Bit Event Counter PACT Prescaled Clock...
Page 450: Command And Definition Area
Command And Definition Area Virtual Timer Definition Maximum Virtual Timer Value “0” Virtual Timer Value “0” D31........D23 D22...D20 D15........D1 Requires two time slots. 01F3h D0 must be written as 0 to get a valid timer definition. D1–15 Virtual timer value Provides the most significant 15 bits of a 16-bit virtual timer.
Page 451: Sci Baud Rate Timer Definition
SCI Baud Rate Timer Definition Maximum Virtual Timer Value Virtual Timer value D31........D23 D22..D20 D15........D1 Requires two time slots. = 0 D0 must be written as 0 to get a valid timer definition D1–15 Baud rate timer Provides the most significant 15 bits of a 16-bit virtual timer used as the baud rate generator.
Page 452: Offset Timer Definition - Time From Last Event
Offset Timer Definition - Time From Last Event Maximum Event Virtual Timer Offset Counter Value Value “1” D31......D24 D15......D1 Requires two time slots if bit D21 =0. Requires three time slots if bit D21 =1. D0 must be written as 1 to get a valid timer definition. D1–15 Virtual timer offset value Provides the most significant 15 bits of a 16-bit virtual timer offset.
Page 453: Standard Compare Command
Standard Compare Command Timer Reserved ”0” ”0” Select Compare Value D31..D28 D20..D18 D15....D0 Requires one time slot. D0–15 Timer compare value Provides a 16-bit timer compare value. This timer value is either the last virtual timer defined above this command in the command/definition area or, if no virtual timer has been defined, the default timer (reference timer).
Page 454: Conditional Compare Command
Conditional Compare Command Event Counter Timer Compare Value ”1” Pin Select Compare Value D31......D24 D20..D18 D15..........D0 Requires one time slot. D0–15 Timer compare value Provides a 16-bit timer compare value. This timer value is compared to either the last virtual timer defined above this command in the command/definition area or, if no virtual timer has been defined, the default timer (reference timer).
Page 455: Double Event Compare Command
Double Event Compare Command Event 2 Event 1 Comp. Comp. Reserved ”0” ”1” Select Value Value D20...D18 D15..D8 D7..D0 Requires one time slot. D0–D7 Event 1 Sets an 8-bit value which, when matched by the 8-bit event counter, causes the action defined by D17, D21, and D29.
Page 456: Pact Control Registers
PACT Control Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PACTSCR DEFTIM DEFTIM CMD/DEF FAST PACT PACT PACT PACT P040 OVRFL OVRFL AREA MODE PRESCALE PRESCALE PRESCALE PRESCALE INT ENA INT FLAG SELECT SELECT3 SELECT2...
Page 457: Interrupt Vector Sources
Interrupt Vector Sources MODULE VECTOR INTERRUPT INTERRUPT SYSTEM PRIORITY ADDRESS SOURCE FLAG INTERRUPT IN GROUP PACT 7FB0h,7FB1h PACT Circular Buffer BUFF INT FLAG BUFINT (Group 1) 7FB2h,7FB3h PACT CP6 Edge CP6 INT FLAG CP6INT 7FB4h,7FB5h PACT CP5 Edge CP5 INT FLAG CP5INT 7FB6h,7FB7h PACT CP4 Edge...
Page 458 Part III Module Specific Application Design Aids Part III contains six sections: RESET Operations ....SPI and SCI Modules ....Timer and Watchdog Modules .
Page 460: Proper Termination Of Unused I/O Pins
Proper Termination of Unused I/O Pins Michael S. Stewart Microcontroller Products — Semiconductor Group Texas Instruments...
Page 462: Introduction
Introduction Occasionally, embedded microcontroller systems applications do not require the use of all the I/O pins available on the chosen microcontroller. In this case, the design engineer must properly terminate all unused I/O pins to ensure proper device operation. The main area of concern regarding proper pin termination is power consumption in low-power modes (standby or halt).
Page 463: Pull Low Through A Resistor
Figure 1. Best Solution for Terminating Unused I/O Pins: Pull Low Through a Resistor TMS370 Microcontroller Unused pin 10 kΩ † Note minimum Note†: To reduce EMI emissions, keep the loop area as small as possible. NOTE: The above solution is the best recommendation for unused I/O pins.
Page 464: What To Do: Alternative Solutions
Figure 2. Recommended Termination for the XTAL1 Pin When Used in the Externally Driven Clock Mode. TMS370 Microcontroller XTAL1 pin 50 pF † Note typical Note†: To reduce EMI emissions, keep the loop area as small as possible. What to Do: Alternative Solutions Alternative solutions exist for terminating unused I/O pins.
Page 465: Alternate Solution For T Erminating Unused I/O Pins: Open Circuit
Figure 3. Alternate Solution for Terminating Unused I/O pins: Open Circuit. TMS370 Microcontroller No Connect Unused pin Another solution is to initialize all unused input and bidirectional I/O pins as inputs and tie all these pins low via one external resistor (10 kΩ or greater). The main advantage of this solution is its minimal additional system cost.
Page 466: Summary
Figure 4. Alternate Solution for Terminating Unused I/O Pins: Shared Pull-Down Resistor. TMS370 Microcontroller Unused pin n Unused pin 2 Unused pin 1 10 kΩ † Note minimum Note†: To reduce EMI emissions, keep the loop area as small as possible. Summary The best overall solution for terminating unused I/O pins (input only or bidirectional) is to tie each unused pin individually low through a resistor.
Page 468: Part Iv: Eeprom Programming
Part IV EEPROM Programming Part IV contains two sections: EEPROM Self Programming ..Bootstrap Programs ....
Page 470: Eeprom Self Programming
EEPROM Self Programming With the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 472: Programming With The Tms370 Family
Programming With the TMS370 Family The following example demonstrates the self-programming ability of the TMS370 family. This feature can program any byte of the onboard data EEPROM by passing the appropriate data and address to this routine. The program consists of two major sections: the procedure that determines the bits that need to be changed (PROGRAM), and the procedure that changes these bits (EEPROG).
Page 473: Eeprog Routine
LASTCHK ;Are there any 1s to program? WRITE1 #3,ECOM ;DEECTL value=3 (program 1s) TEMP2,A CALL EEPROG ;Program 0s ;Verify the programming operation. LASTCHK MOV @ADDR1,A ;Check new memory against wanted ;memory. TEMP2,A ;If equal then exit. EXITW Error–handling routine here EXITW EEPROG Routine EEPROG...
Page 474 WRITE1 #3,ECOM DEECTL value=3 (program 1s) TEMP2,A x1010 CALL EEPROG x1010 Program 0s. Verify the programming operation. LASTCHK *ADDR1,A x1010 Check new memory against wanted memory. TEMP2,A If equal then exit. EXITW Error–handling routine here EXITW...
Page 476: Bootstrap Programs
Part IV EEPROM Programming Part IV contains two sections: EEPROM Self Programming ..Bootstrap Programs ....
Page 478: Bootstrap Program For The Tms370
Bootstrap Program for the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 480 Bootstrap Program This is a bootstrap program for TMS370. This program is resident in master. It is transmitted to slave mode in RAM memory. After transmission, the control is passed on to the beginning of this program in slave mode at 20h. This programs data EEPROM. It checks the first word for the EEPROM command and the number of bytes to be programmed.
Page 481 DINT #3,A ;Program DEECTL=0 (program 1s). CALLR PROG ;Do the write operation. CALLR LASTCHK ;Check the programmed byte with desired. INCW #1,DATAL+2 ;Go to next location. DJNZ TEMP,LOOP1X ;Do until all bytes done. LOOP2X BTJZ #40H,SPICTL,LOOP2X ;Check if character received. SPIBUF,A ;Read received character.
Page 482: Bootstrap Program For The Spi In Slave Mode
Bootstrap Program for the SPI in Slave Mode Microcontroller Products—Semiconductor Group Texas Instruments...
Page 484 Bootstrap Program for the SPI in Slave Mode This program executes on a serial peripheral interface (SPI) operating in the slave mode. The SPI is first initialized by the INIT routine (see code below), then control transfers to the main program at 7000h. When the SPI interrupt occurs, it sets the number of bootstrap-program bytes into register B, then loads in the program starting at address 0020h, checking the SPI INT FLAG (bit 6 of the SPICTL register) to know when each byte is received.
Page 486: Bootstrap Program For The Tms370 In Master
Bootstrap Program for the TMS370 in Master Microcontroller Products—Semiconductor Group Texas Instruments...
Page 488 Introduction This program is a master program and is resident in master MCU. It transmits another program from master to slave MCU. It is mainly for programming data EEPROMs in slave mode. It is assumed that the slave MCU has a bootstrap program for receiving the data from the SPI. Routine ;Define the registers SPICCR...
Page 489 ;Initialize the registers for program EEPROM programming. MOVW #7000H,REALST ;Load beginning of real data to be ;transmitted. MOVW #7000H,STRT ;Starting address of data in slave. MOVW #0400H,LENGTH ;Length of data. CALL MAINPROG ;Go to main program. ;Initialize registers for data EEPROM programming. MOVW #2000H,REALST ;Load beginning of real data to be...
Page 490 ;Subroutine PROG2 creates a command word and transmits the bytes when total ;number of bytes in a packet is less than 3F hex. PROG2 TEMP2,COMMAND ;Load number of bytes to be transmitted. CALL TRANSMIT ;Go to transmit program. ;Initialize index. START2 CALL SPISE...
Page 492: Part V: External Memory Expansion Examples
Part V External Memory Expansion Examples...
Page 494: Using Memory Expansion In Microcomputer Mode With Internal Memory Disabled
Using Memory Expansion in Microcomputer Mode With Internal Memory Disabled Microcontroller Products—Semiconductor Group Texas Instruments...
Page 496: Introduction
Introduction This report describes special features of the digital I/O port control registers (address range 1020h to 102Fh), not fully documented in the TMS370 Family User’s Guide. These features should be taken into account when memory expansion is used in microcomputer mode to prevent any uncontrolled effect.
Page 498: Interfacing And Accessing External Memory
Interfacing and Accessing External Memory Microcontroller Products—Semiconductor Group Texas Instruments...
Page 500: Microcomputer Interface Example
Microcomputer Interface Example The following exercise is one method of interfacing the TMS370 family with common memory. The goals of this example include the following: Interfacing with the maximum amount of memory Using the least expensive logic elements Using a minimum amount of parts Maintaining sufficient system speed The example shown in Figure 1 illustrates a balance of these goals.
Page 501: Microcomputer Interface Example
Figure 1. Microcomputer Interface Example V CC 10 kΩ (All) CSE2 CSE1 CSPF CSH3 CSH2 CSH1 ROM1 ROM2 ROM3 RAM1 RAM2 V CC V SS V SS V SS Address 0–14 Data 0–7 U1 = TMS370Cx5x 8-Bit Microcontroller U2, U3, U4 = TMS27C256 32K x 8 EPROM V SS U5 = Unspecified 64-Byte Peripheral U6, U7 = 8K x 8 Static RAM...
Page 502: Wait State Control Bits
Table 2. Timing Specifications for the HM6264P-15 RAM Device Symbol Description Address access time — 150 ns Out disable to output in high Z Chip selection to output — 150 ns Chip deselection to output in high Z 0 ns 50 ns Chip select to end of write 100 ns...
Page 503: Read Cycle Timing
Table 4. Memory Interface Timing Symbol Description Unit t c † CLKOUT (system clock) cycle time 2000 t w(COL) CLKOUT low pulse duration 0.5 t c – 25 0.5 t c t w(COH) CLKOUT high pulse duration 0.5 t c 0.5t c + 20 t d(COL–A) Delay time, CLKOUT low to address R/W, and OCF valid...
Page 504: Chip Select Low To Data Read Requirements
Figure 2. Valid Address-to-Data Read Timing t d(AV-DV)R Valid Address on Bus (From TMS370) Data on Bus (From Memory) Data Required by TMS370 (From Memory) Table 5. Address-to-Data Timing Specifications Symbol Description Formula Time TMS370 (0 wait) requires data 1.5 t –...
Page 505: Chip Select High To Next Data Bus Drive Requirements
Figure 3. Chip-Select Low-to-Data Read Timing t d(EL-DV) t a(E) EDS/CSxx t C01 (From TMS370) Data on Bus (From Memory) Data Required by TMS370 (From Memory) Table 6. Chip-Select Low-to-Data Read Timing Specifications Name Description Formula Time TMS370 (0 wait) requires data –...
Page 506: Read Data Hold After Chip Select High Requirements
Table 7. Chip-Select High-to-Next Data Bus Drive Timing Specifications Name Description Formula Time TMS370 (all) drives memory 1.2 5t – 40 210 ns d(EH–D) TMS27C256-25 releases memory 60 ns HM6264-15 releases memory 50 ns Read Data Hold After Chip Select High Requirements The high transition of the chip-select signal (CHxx) indicates the end of a data transfer (in this case, a read) cycle.
Page 507: Write Cycle Timing
Write Cycle Timing The write cycle timing is defined primarily by the characteristics of the RAM interfacing with the TMS370. The Hitachi HM6264 used in this example offers two types of write cycles. This application uses a write cycle in which the output enable pin (OE) is always fixed low. With the CS2 pin tied to V , the CS1 and R/W signals determine the read and write cycle boundaries.
Page 508: Design Options
Data Hold After Chip-Select High The TMS370 must hold valid data on the bus until the RAM no longer needs it; otherwise, incorrect data may be written into the RAM. Most RAMs do not need data present on the pins following the chip-select’s high transition.
Page 509: Bank Switching Examples
output lines from the TMS370 to the EPROM’s E pin. The pins should be software enabled before the EPROM’s program is entered. Access time from address to valid data: TMS370 (no wait) requires data 1.5 t – 115 185 ns D(AV–DV)R TMS27C256-17 provides data 170 ns (ok)
Page 510: Equates For Examples
Figure 8. Peripheral File Frame 2: Digital Port Control Registers Designation ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APORT1 1020h P020 Reserved Port A Control Register 2 APORT2 1021h P021 ADATA 1022h P022...
Page 511: Coding
Table 12. Port Configuration Registers Set-Up MC Pin High When RESET Goes High MC Pin Low When RESET Goes High General-Purpose I/O Use † Microcomputer Mode † DPORT1 =0 DPORT1 =0 DPORT1 =0 DPORT1 =1 xPORT2 = 0 xPORT2 = 0 xPORT2 = 1 xPORT2 = 1 Micro-...
Page 512: Changing To Eprom Bank 2
#0E7h,P02E ;Set all CSxx to 1 when CSxx ;are outputs #0D0h,DPORT2 ;Enable CSH1, CSE1, and ;R/W functions. #0E7h,P02F ;Turn all chip selects to outputs. ;Pull-up resistors are important ;for power-up since CSxx are high- ;impedance floating inputs. Changing to EPROM Bank 2 Routine This program illustrates how to change the EPROM bank without affecting the RAM banks.
Page 514: Read/Write Serial Eeprom Data On The Tms370
Read/Write Serial EEPROM Data on the TMS370 Microcontroller Products—Semiconductor Group Texas Instruments...
Page 516 Introduction This routine reads and writes to the EEPROM, computes the checksum on the first seven bytes of data and places the checksum in the eighth byte. These are conditions for the read/write serial EEPROM data routine: 1. The delay timing is based on a 5 MHz SYSCLK. 2.
Page 517 Read/Write Serial EEPROM Data Routine ;REGISTER FILE EQUATES EEPROM .EQU R010 ;8 BYTES OF EEPROM DATA EEPFLG .EQU R018 ;EEPROM FLAGS ; PERIPHERAL FILE EQUATES DPORT .EQU P02E ;I/O PORT .EQU P02F ;DATA DIRECTION REGISTER ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;READ EEPROM RDEEP CALL SELEEP ;STROBE OUT 0s TO EEPROM #64,B...
Page 518 RDXIC CALL XICINS RDDAT #16,B RDDAT1 BTJZ #00000100b,DPORT,RDDAT2 SETC RDDAT2 CALL SHFTNV CALL CLKZRO DJNZ B,RDDAT1 DESEEP ;DESELECT EEPROM & RETURN. ;WRITE EEPROM ;THIS ROUTINE COMPUTES THE CHECKSUM ON THE FIRST 7 BYTES OF ;EEPROM AND PLACES THAT IN THE 8TH BYTE. THE 8 BYTES ARE THEN ;WRITTEN TO EEPROM LOCATIONS 0–3.
Page 519 EEPROM+6,A ;WRITE INSTUCTION TO NATIONAL PART, THEN SEND DATA, DELAY WTNAT CALL NATINS CALL WTDAT CALL DESEEP CALL DL30MS ;DESELECT FOR 30 MILLISECONDS. CALL SELEEP DESEEP DL30MS CALL DL10MS ;30 MILLISECOND DELAY CALL DL10MS DL10MS #2,A ;10 MILLISECOND DELAY DL10M1 DJNZ B,DL10M1 DJNZ...
Page 520 SELEEP #00000010b,DPORT CLKZRO ;DESELECT EEPROM DESEEP #11111101b,DPORT ;CLOCK A ZERO BIT TO EEPROM CLKZRO #11111110b,DPORT CLKEEP #00001000b,DPORT #11110111b,DPORT ;SHIFT EEPROM DATA LEFT 1 BIT ;LEAVES BIT SHIFTED OUT IN CARRY, SHIFTS CARRY VALUE ON CALL INTO ;LAST BIT OF EEPROM SHFTNV .EQU EEPROM+7...
Page 522: Part Vi: Specific System Application Design Aids
..... . Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers ..
Page 524: Pcb Design Guidelines For Reduced Emi
PCB Design Guidelines for Reduced EMI Robert DeMoor Microcontroller Products—Semiconductor Group Texas Instruments...
Page 526: Overview
Overview Electromagnetic interference (EMI) often seems like a mysterious phenomenon. EMI can be difficult to control, and even the results of EMI testing can vary from day to day and from test facility to test facility. The act of controlling EMI has been called black magic or voodoo. However, EMI has been researched for many years, and guidelines have been established that can improve the electromagnetic compatibility (EMC) of systems to which they are applied.
Page 527: Loops And Antennas
Figure 1. EMI Sources, Paths, and Receivers Sources Paths Receivers Radiated ICs, Circuit Boards Oscillators Digital ICs Radio Tuners Conducted Switching Cellular Phones Regulators Antennas (Screen room) Resonant Components The receiver can be a sensitive electronic module, such as a radio, or it can be an antenna specifically designed to receive electromagnetic emissions in a test environment.
Page 528: The Loop: Current Flow Path
The Loop: Current Flow Path Current must flow in a loop. If the loop is broken, the same current will no longer flow. Current flowing through a loop generates electric and magnetic fields, with field strength proportional to loop size and to the square of the frequency for loops that are smaller than 1/4 of the wavelength of the frequency of interest [3].
Page 529: Differential Mode And Common Mode Radiation
return path. Thus, the loop area associated with a signal and its return is the loop between the signal and its lowest-impedance ground path. This area must be carefully controlled. PCB traces carrying high frequencies, large voltage swings, or large amounts of current are the most serious EMI offenders.
Page 530: Coupling
PCB. These cables look like monopole antennas in the EMI world. The cables radiate electric fields and are driven by the noise on the PCB’s ground system. Figure 4. Common-mode Radiation I / O Cable I / O Common mode noise can be controlled by lowering the source potential, which usually is that of the ground system.
Page 531: High-Frequency Characteristics Of Passive Devices
High-Frequency Characteristics of Passive Devices A misconception about PCB design is that the location of components does not matter as long as they are connected according to the schematic. Unfortunately, circuit elements are not always what they seem to be. For instance, at high frequencies, a capacitor becomes more inductive than capacitive due to the inductance of the leads and the PCB trace.
Page 532: Pcb Design Implementation
PCB Design Implementation The implementation of PCB design guidelines to circuit board layout is critical for achieving electromagnetic compatibility (EMC). Furthermore, it is most cost-effective to design a PCB for EMC at the beginning of the design cycle since later changes to improve EMC become more difficult and costly. However, there is little or no cost involved with implementing PCB design guidelines for reduced EMI at the beginning of the design cycle.
Page 533: Space For Ground Structures
Figure 7. PCB Zoning Analog Noisy µC Digital Space for Ground Structures An important aspect of board zoning is to allow space for proper grounding. Space for grounding should be provided before the placement of IC’s and components is finalized. Grounding is an extremely important facet of PCB design, but its importance is sometimes overlooked.
Page 534: Digital: Grid The Ground
current for the high frequencies will follow a path directly under the signal and back to the source. While a ground plane is ideal for minimizing loop area and impedance, it will not always solve capacitive or inductive coupling problems. A ground grid for digital circuitry can provide low-impedance signal return paths for high-frequency noise on a two-layer board and does not require the additional cost of a ground plane, which usually requires at least a four-layer PCB.
Page 535: Ground Grid
Figure 8. Ground Grid Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î...
Page 536: Micro Ground
Figure 9. Micro-ground Bypass Capacitor Ferrite Oscillator Capacitors Bottom In this example, the topside layer of the PCB is on the left, and the bottom side is on the right. The topside traces are shown in dotted line form on the bottom side diagram for alignment purposes. Notice how the oscillator capacitors are located on the inside of the resonator in order to reduce loop area.
Page 537: Analog Ground
“The design of an effective ground grid on a PCB is a critical aspect to the regulatory compliance of the PCB and its host system” [2]. Analog Ground It is important to distinguish between analog and digital grounds. Digital grounds should be designed to return high frequencies through a low impedance path, and analog grounds should be designed to return low frequency current or dc to its origin through a low-resistance path.
Page 538: Low Impedance Ground Node
traces at all. Thin ground traces can still reduce loop areas, whereas an absence of ground traces can result in large loops. One approach for designing a two-layer board is to lay down a thin-traced ground grid, making routes wider along high-current paths, and to increase the width of the traces, where possible, after routing all of the other signals.
Page 539: Clock Lines
routing a ground on each side of these fast signals provides a good signal return while also providing some shielding for the nearby signals. Additionally, routing fast signals to connectors (and wiring harnesses), or routine adjacent to other signals that are routed to connectors should be avoided. The fast signal lines should also be properly bypassed, as discussed later.
Page 540: Bypassing
the PCB (that is, diodes, MOVs, and large capacitors), which usually should be located near the power and/or signal connectors on the PCB. Avoid chopping up (making gaps) in the ground plane by placing signal traces on it. When the return current (GND current) cannot follow the path of least impedance (the same path as the associated signal), radiating loops are created.
Page 541: Power Bypassing: Vcc/Vss, Vcc3/Vss3
should be bypassed to V . Similarly, the analog supply (V ) should be bypassed only to analog ground (V Since V and V supply the current to the digital logic, they contain the most high-frequency elec- tromagnetic energy of any pins on a device. Thus, the loops created by V and V should receive the most attention with regard to placement of the capacitors and the loops created by their connections.
Page 542: Summary
Summary By understanding and applying a few fundamental PCB design guidelines, a designer can reduce the radiated EMI of a system inexpensively at the beginning of the design cycle. Following is a summary of PCB design guidelines for reduced EMI: 1.
Page 543: References
3. Ott, Henry W., Noise Reduction Techniques In Electronic Systems, second edition, John Wiley & Sons, New York, 1988. 4. Schneider, John, Automotove PCB Design Guidelines for Reduced EMI, Texas Instruments, 1992 5. Van Doren, Tom, Grounding and Shielding Electronic Systems, T. Van Doren, 1993.
Page 544: Cost Effective Input Protection Circuitry For The Texas Instruments
..... Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers ..
Page 546: Cost Effective Input Protection Circuitry For The Texas Instruments
Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers David T. Maples Michael S. Stewart Microcontroller Products—Semiconductor Group Texas Instruments...
Page 548: Introduction
Introduction The Texas Instruments TMS370 microcontroller family has been designed to reduce the system cost of external input protection circuitry. Features of the TMS370 family that allow this cost advantage include: TTL specified I/O levels Internal diode protection circuitry Today’s microcontroller based systems are subjected to electrically harsh environments that require the existence of input protection circuitry.
Page 549: Indeterminate Range For Ttl And Cmos
Figure 1. Indeterminate Range for TTL and CMOS Input Thresholds (V = 5 V) TTL Input Threshholds (V CC = 5.0 V) CMOS Input Threshholds (V CC = 5.0 V) V IH = 3.5 V V IH = 2.0 V Indeterminate Range Indeterminate Range V IL = 1.0 V...
Page 550: Switching To Vehicle Ground
Figure 3. Switching to Vehicle Ground Input µC Input Conditioning The voltage divider circuit is probably the simplest and most cost effective place to start the design of the input conditioning circuitry. Figure 4 illustrates the function of a simple voltage divider circuit with the TMS370 I/O buffer circuitry.
Page 551: Tms370 Microcontroller Buffer Circuitry With External Voltage Divider Circuitry
Figure 4. TMS370 Microcontroller Buffer Circuitry With External Voltage Divider Circuitry Vehicle Battery (V bat ) Switch to V V CCD V CCD I PIN External Conditioning µC Input Circuitry Switch to ground V CC V CC V CC I PIN µC Input External Conditioning Circuitry...
Page 552: Designing With Competitors Cmos Specified Level Inputs
Designing With Competitors CMOS Specified Level Inputs Consider the CMOS input levels of most standard microcontrollers. Table 2 illustrates the conditions that the input conditioning circuitry will be exposed to and the requirements it must satisfy. Table 2. Typical CMOS Parameters and System Conditions Parameter Value Normal battery range (switch to V bat condition)
Page 553: Designing With Ti's Ttl Level Cmos Inputs
guaranteed to recognize as a logic 1 or logic 0. Therefore, for all valid voltages that the input conditioning is exposed to (such as 9 V to 18 V for an automotive switch to battery condition), the resistor curves must fall within the logic 1 or logic 0 range to satisfy the design constraints.
Page 554: Ttl Input Levels Over Variations In Normal Vbat
Figure 6. TTL Input Levels Over Variations in Normal V Switch to Switch to Battery Ground Clamp Diodes Conducting 1/3 ratio V IN Max 1/4 ratio 1/5 ratio Logic 1 TTL V IH Indeterminate TTL V IL Region Logic 0 V IN Min.
Page 555: External Electrical Noise Suppression Circuitry
Figure 7. External Electrical Noise Suppression Circuitry V CC V CC µC Input V CC µC Input 5.1 V Diode-protected Battery µC Input The external noise suppression circuits illustrated in Figure 7 are necessary for over voltage protection. However, the TMS370 microcontroller family has been designed with internal diode protection circuitry. A simple calculation can provide the necessary value for an external current limiting resistor that, coupled with the internal diode protection circuitry, can adequately protect the TMS370 microcontroller from external high voltage spikes.
Page 556: Tms370 Based External Noise Suppression Circuitry
Figure 8. TMS370 Based External Noise Suppression Circuitry Vehicle Battery (V bat ) V CCD V CCD I PIN External Conditioning µC Input Circuitry The system cost advantages of designing with the TMS370 family of microcontrollers becomes quite evident when compared to competitive microcontrollers that do not contain internal diode protection circuitry or TTL input levels.
Page 557: Tms370 Microcontroller I/O Pin Buffer Types
60% silicon. The original TMS370 was a 2-micron process (100%). The 80% shrink is a redesign for a 1.6 micron process. Likewise, the 60% shrink is a redesign for a 1.2 micron process. The 1.2 micron silicon is typically provided for new applications. The internal diode protection circuitry is identical for both 1.2 and 1.6 micron devices.
Page 558: Tms370 Simplified 1.2 Micron And 1.6 Micron Silicon Buffer Circuitry
Figure 9. TMS370 Simplified 1.2 Micron and 1.6 Micron Silicon Buffer Circuitry V CC V CC Pin Data 300 Ω 8 kΩ Output Fast Input Slow I/O Enable 30 Ω 20 Ω 20 Ω V CC V CC Pin Data 400 Ω...
Page 559 Solving for R2 to protect against a positive (+ 150 V) voltage spike: GIVEN: + 150 V 5.5 V (Worst case for this example. A value of 4.5 V would allow a larger voltage drop across the internal resistance) 7.0 V (Absolute maximum value) Solve for V –...
Page 560: Typical Values Of R2 Required For 1.2 And 1.6 Micron Silicon
(R3 + R2) R3 = Ω R3 = 191 k Ω R3 = 64 k The TMS370 can withstand voltage transients and interpret vehicle battery variations as logic 1s or logic 0s using a simple voltage divider. The series current limiting resistor (R2) limits the voltage and current seen on the I/O pins such that the internal diode protection circuitry can withstand the defined system transients.
Page 561: External Resistance (R2) Values For Various External
1 µs per 1 kΩ of source impedance. The system designer has to determine the appropriate value to meet system requirements. Cost Analysis This report establishes that Texas Instruments TMS370 microcontroller family devices input circuitry is more robust than competitors’ input circuitry, and allows system designers to simplify their external...
Page 562 Figure 11 illustrates the simple resistor divider input conditioning circuit for Texas Instruments TMS370 family TTL inputs, as well as other external protection circuits such as external diodes, external zener, transistor level shifter,...
Page 563: Examples Of External Protection Circuitry
Figure 11. Examples of External Protection Circuitry Vehicle Battery (V bat ) TI’s TTL Input Vehicle Battery (V bat ) V CC TTL Input Without Internal Clamp Diodes Vehicle Battery (V bat ) TTL Input Without Internal Clamp Diodes 5.1 V Vehicle Battery (V bat ) V CC CMOS Input...
Page 564: Cost Comparison
1 and 0 input voltages across all valid vehicle voltages. There is a cost savings over the CMOS voltage levels by using a simple resistor divider instead of active circuitry. Likewise, Texas Instruments TMS370 family of microcontrollers allows system designers to use the internal diode protection circuits to withstand voltage transients with a simple resistor divider.
Page 565: References
References 1. Texas Instruments,TMS370 Family Data Manual, pg. 16–18, 1993 2. Motorola Corp., MC68HC11E9 Data Sheet, Appendix A, pg. 2, April 1992 3. Motorola Corp., 80C51 Data Sheet, pg. 13–3, March 1992 4. Phillips Semiconductor Corp., 80C51 Data Sheet, pg. 142, Jan 26, 1993 5.