Texas Instruments RM48 series Technical Reference Manual
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Texas Instruments RM48 series Technical Reference Manual

16/32-bit risc flash microcontroller
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Table of Contents

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RM48x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual
Literature Number: SPNU503C
March 2018

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Summary of Contents for Texas Instruments RM48 series

  • Page 1 RM48x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual Literature Number: SPNU503C March 2018...

  • Page 2: Table Of Contents

    Disabling a Power Domain Permanently ................3.3.5 Changing Power Domain State ....................3.3.6 Reset Management ..............3.3.7 Diagnostic Power State Controller (PSCON) ..................3.3.8 PSCON Compare Block Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 3 F021 Flash Module Controller (FMC) ........................Overview ......................5.1.1 Features ....................5.1.2 Definition of Terms ....................5.1.3 F021 Flash Tools ..................... Default Flash Configuration ........................SECDED ................... 5.3.1 SECDED Initialization SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 4 5.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) ..... 5.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) ....... 5.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 5 7.5.11 ROM Algorithm Mask Register (ALGO) ..............7.5.12 RAM Info Mask Lower Register (RINFOL) ..............7.5.13 RAM Info Mask Upper Register (RINFOU) ..................PBIST Configuration Example SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 6 10.4.2 Behavior on Oscillator Failure ................10.4.3 Recovery from Oscillator Failure ................... 10.4.4 LPOCLKDET Enable ..................10.4.5 LPOCLKDET Disable ................10.4.6 Trimming the HF LPO Oscillator ......................... 10.5 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 7 12.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1) ............12.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1) ............12.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1) SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 8 13.3.20 RTI Update Compare 2 Register (RTIUDCP2) ..............13.3.21 RTI Compare 3 Register (RTICOMP3) ............13.3.22 RTI Update Compare 3 Register (RTIUDCP3) ..........13.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 9 14.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) ..........14.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ......14.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 10 15.8.7 FIQ Index Offset Vector Registers (FIQINDEX) ............15.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2]) ..........15.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2]) ............15.8.10 Interrupt Enable Set Registers (REQENASET[0:2]) Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 11 ..................17.2.11 EMIF Signal Multiplexing ....................17.2.12 Memory Map ..................17.2.13 Priority and Arbitration ..................17.2.14 System Considerations ..................17.2.15 Power Management ..................17.2.16 Emulation Considerations SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 12 18.3.25 POM Component ID 1 Register (POMCOMPONENTID1) ..........18.3.26 POM Component ID 2 Register (POMCOMPONENTID2) ..........18.3.27 POM Component ID 3 Register (POMCOMPONENTID3) ................Analog To Digital Converter (ADC) Module Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 13 ..................19.9.3 ADC Results’ RAM Parity ............... 19.10 ADEVT Pin General Purpose I/O Functionality .................... 19.10.1 GPIO Functionality ....................... 19.10.2 Summary ....................19.11 ADC Control Registers SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 14 19.11.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) ....... 19.11.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ....... 19.11.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 15 ............... 20.4.10 Interrupt Priority Register (HETPRY) ................20.4.11 Interrupt Flag Register (HETFLG) ..............20.4.12 AND Share Control Register (HETAND) ..............20.4.13 HR Share Control Register (HETHRSH) SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 16 21.2.1 Data Transfers between Main RAM and N2HET RAM ..............21.2.2 Arbitration of HTU Elements and Frames ..............21.2.3 Conditions for Frame Transfer Interruption ..............21.2.4 HTU Overload and Request Lost Detection Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 17 Overview 1018 ....................... 22.2 Quick Start Guide 1019 ................22.3 Functional Description of GIO Module 1021 ....................22.3.1 I/O Functions 1021 ..................... 22.3.2 Interrupt Function 1022 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 18 Message Object Configurations 1061 ............. 23.7.1 Configuration of a Transmit Object for Data Frames 1061 ..........23.7.2 Configuration of a Transmit Object for Remote Frames 1061 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 19 ..............23.17.8 Core Release Register (DCAN REL) 1089 ............23.17.9 Auto-Bus-On Time Register (DCAN ABOTR) 1090 ..........23.17.10 Transmission Request X Register (DCAN TXRQ X) 1090 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 20 Low-Power Mode 1142 ......................... 24.6 Interrupts 1143 ................24.6.1 Interrupts in Multi-Buffer Mode 1143 ......................24.7 DMA Interface 1145 ..................24.7.1 DMA in Multi-Buffer Mode 1145 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 21 24.10 Multi-Buffer RAM 1214 ............... 24.10.1 Multi-Buffer RAM Auto Initialization 1215 ..............24.10.2 Multi-Buffer RAM Register Summary 1215 ............ 24.10.3 Multi-Buffer RAM Transmit Data Register (TXRAM) 1216 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 22 ...................... 25.10 LIN Configurations 1268 ....................25.10.1 Receiving Data 1268 .................... 25.10.2 Transmitting Data 1269 ....................... 25.11 Low-Power Mode 1270 ..................25.11.1 Entering Sleep Mode 1270 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 23 26.2.3 SCI Baud Rate 1329 ............... 26.2.4 SCI Multiprocessor Communication Modes 1329 ......................26.3 SCI Interrupts 1332 ..................... 26.3.1 Transmit Interrupt 1333 ....................26.3.2 Receive Interrupt 1333 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 24 27.2.4 I2C Module Start and Stop Conditions 1377 ................... 27.2.5 Serial Data Formats 1377 ..................27.2.6 NACK Bit Generation 1379 ....................27.3 I2C Operation Modes 1380 ..................27.3.1 Master Transmitter Mode 1380 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 25 28.1.1 Purpose of the Peripheral 1410 ......................28.1.2 Features 1410 ..................28.1.3 Functional Block Diagram 1411 .............. 28.1.4 Industry Standard(s) Compliance Statement 1412 ......................28.2 Architecture 1412 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 26 28.5.1 Transmit Revision ID Register (TXREVID) 1488 ..............28.5.2 Transmit Control Register (TXCONTROL) 1488 ............28.5.3 Transmit Teardown Register (TXTEARDOWN) 1489 ..............28.5.4 Receive Revision ID Register (RXREVID) 1489 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 27 29.2.2 USB Host Controller Differences From OHCI Specification for USB 1534 ............29.2.3 Implementation of OHCI Specification for USB 1535 ................29.2.4 USB Host Controller Registers 1536 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 28 30.1.2 Block Diagram 1660 ....................... 30.2 Module Operation 1661 ....................30.2.1 Data Format 1661 ....................... 30.2.2 Data Port 1663 ....................30.2.3 Error Handling 1664 ....................... 30.2.4 Interrupts 1665 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 29 31.4.13 RTP Pin Control 5 Register (RTPPC5) 1729 ..............31.4.14 RTP Pin Control 6 Register (RTPPC6) 1730 ..............31.4.15 RTP Pin Control 7 Register (RTPPC7) 1732 SPNU503C – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 30 32.4.3 EFC Error Status Register (EFCERRSTAT) 1741 ............... 32.4.4 EFC Self Test Cycles Register (EFCSTCY) 1741 ............32.4.5 EFC Self Test Signature Register (EFCSTSIG) 1742 ........................Revision History 1743 Contents SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 31 ..........2-44. System Software Interrupt Request 3 Register (SSIR3) [offset = B8h] ........... 2-45. System Software Interrupt Request 4 Register (SSIR4) [offset = BCh] SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 32 2-91. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) [offset = A8h] ........2-92. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) [offset = ACh] ...................... 3-1. PMM Block Diagram ..................... 3-2. Core Power Domains List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 33 ........5-13. Flash Correctable Error Position Register (FCOR_ERR_POS) [offset = 18h] ....... 5-14. Flash Error Detection and Correction Status Register (FEDACSTATUS) [offset = 1Ch] SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 34 6-12. TCRAM Module Parity Error Address Register (RAMPERRADDR) [offset = 3Ch] ........6-13. Auto-Memory Initialization Enable Register (INIT_DOMAIN) [offset = 40h] ....................7-1. PBIST Block Diagram List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 35 10-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = FF2Ch] ......................10-9. Basic PLL Circuit ........................ 10-10. PFD Timing ..................10-11. PLL Modulation Block Diagram SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 36 12-30. ESM Interrupt Enable Clear Register 4 (ESMIECR4) [address = FFFF F54Ch] ........12-31. ESM Interrupt Level Set Register 4 (ESMILSR4) [address = FFFF F550h] List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 37 13-45. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h] ......13-46. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] ............. 13-47. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h] SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 38 14-43. Data Bus Selection Register (CRC_TRACE_BUS_SEL) [offset = 140h] ................. 15-1. Device Level Interrupt Block Diagram ................. 15-2. VIM Interrupt Handling Block Diagram ....................15-3. VIM Channel Mapping List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 39 16-10. Example of Priority Queues ..................16-11. Example Channel Assignments ..................16-12. Example of DMA Data Unpacking ..................16-13. Example of DMA Data Packing ......................16-14. DMA Interrupts SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 40 16-61. RAM Test Control (RTCTRL) [offset = 17Ch] ................16-62. Debug Control (DCTRL) [offset = 180h] ................16-63. Watch Point Register (WPR) [offset = 184h] List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 41 17-22. EMIF Interrupt Raw Register (INTRAW) [offset = 40h] ............. 17-23. EMIF Interrupt Mask Register (INTMSK) [offset = 44h] ........... 17-24. EMIF Interrupt Mask Set Register (INTMSKSET) [offset = 48h] SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 42 19-7. Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC ........19-8. Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 43 19-55. 10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h] ..........19-56. ADC State Machine Status Register (ADSMSTATE) [offset = 88h] ......... 19-57. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch] SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 44 20-5. Multi-Resolution Operation Flow Example .................... 20-6. Debug Control Configuration ....................20-7. Prescaler Configuration ......................... 20-8. I/O Control ..............20-9. N2HET Loop Resolution Structure for Each Bit List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 45 20-55. NHET Interface Block Diagram ............20-56. Global Configuration Register (HETGCR) [offset = 00h] ................... 20-57. Prescale Factor Register (HETPFR) ................. 20-58. N2HET Current Address (HETADDR) SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 46 20-104. HWAG Teeth Number Register (HWATHNB) .............. 20-105. HWAG Current Teeth Number Register (HWATHVL) ..................20-106. HWAG Filter Register (HWAFIL) .................. 20-107. HWAG Filter Register 2 (HWAFIL2) List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 47 20-153. MOV32 Program Field (P31:P0) ..................20-154. MOV32 Control Field (C31:C0) ................... 20-155. MOV32 Data Field (D31:D0) ..............20-156. MOV32 Move Operation for IMTOREG (Case 00) SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 48 21-12. Timing Example for Two WCAP Instructions ................. 21-13. Timing of the WCAP, ECNT, PCNT Example ..............21-14. Global Control Register (HTU GC) [offset = 00] List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 49 22-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h] 1035 ..............22-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h] 1036 .............. 22-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch] 1037 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 50 23-38. Interrupt Pending X Register (DCAN INTPND X) [offset = ACh] 1094 ................ 23-39. Interrupt Pending 12 Register [offset = B0h] 1095 ................ 23-40. Interrupt Pending 34 Register [offset = B4h] 1095 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 51 ........24-13. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) 1131 ................24-14. Block Diagram Shift Register, MSB First 1133 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 52 24-61. Tick Counter Operation 1195 ..............24-62. Tick Count Register (TICKCNT) [offset = 90h] 1195 ..............24-63. Last TG End Pointer (LTGPEND) [offset = 94h] 1196 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 53 25-20. Checksum Compare and Send for Extended Frames 1259 ....................25-21. TXRX Error Detector 1261 .............. 25-22. Classic Checksum Generation at Transmitting Node 1262 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 54 26-9. SCI Global Control Register 1 (SCIGCR1) [offset = 04h] 1341 ............26-10. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] 1344 ............26-11. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] 1346 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 55 ............. 27-27. I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] 1401 ............. 27-28. I2C Peripheral ID Register 2 (I2CPID2) [offset = 38h] 1401 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 56 ......28-36. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 1479 ....28-37. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 1480 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 57 28-84. MAC Address Low Bytes Register (MACADDRLO) 1519 ..............28-85. MAC Address High Bytes Register (MACADDRHI) 1520 ..................28-86. MAC Index Register (MACINDEX) 1520 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 58 ....29-43. DMA Receive Channels Configuration Register (RXDMA_CFG) [address = FCF78A20h] 1583 ....29-44. DMA Transmit Channels Configuration Register (TXDMA_CFG) [address = FCF78A22h] 1584 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 59 ................29-91. Non-ISO TX DMA Done Interrupt Handler 1648 .................... 29-92. ISO TX DMA Start Routine 1650 ................... 29-93. Power Management Signal Values 1652 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 60 31-15. RTP Direct Data Mode Write Register (RTPDDMW) [offset = 2Ch] 1723 .............. 31-16. RTP Pin Control 0 Register (RTPPC0) [offset = 34h] 1724 List of Figures SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 61 ............32-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] 1741 ............32-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] 1742 SPNU503C – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 62 2-45. PLL Control Register 2 (PLLCTL2) Field Descriptions ............2-46. SYS Pin Control Register 10 (SYSPC10) Field Descriptions ..........2-47. Die Identification Register, Lower Word (DIEIDL) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 63 2-94. Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions ........2-95. Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions ........2-96. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 64 4-13. Fault Status Register Field Descriptions ........... 4-14. FAULT_CLEAR_REG: Fault Clear Register Field Descriptions .............. 4-15. Pin Multiplexing Control Registers Field Descriptions ....................4-16. Multiplexing and Control List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 65 5-47. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) Field Descriptions ....5-48. EEPROM Emulation Error Correction Control Register 2 (EE_CTRL2) Field Descriptions ... 5-49. EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) Field Descriptions SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 66 8-12. CPU2 Current MISR Register (CPU2_CURMISR[3:0]) Field Descriptions ........8-13. Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions ..................9-1. Compare Match Test Sequence ................... 9-2. Compare Mismatch Test Sequence List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 67 ........... 12-24. ESM Interrupt Level Clear Register 4 (ESMILCR4) Field Descriptions ............... 12-25. ESM Status Register 4 (ESMSR4) Field Descriptions ......................13-1. RTI Registers SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 68 14-7. CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions ..........14-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions ........... 14-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 69 15-16. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions .............. 15-17. Capture Event Register (CAPEVT) Field Descriptions ................15-18. Interrupt Control Registers Organization ............15-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 70 16-47. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions ........16-48. FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions ........16-49. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 71 17-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..........17-17. Description of the EMIF Interrupt Mask Set Register (INTMSKSET) ..........17-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 72 18-22. POM Peripheral ID 1 Register (POMPERIPHERALID1) Field Descriptions ........18-23. POM Peripheral ID 2 Register (POMPERIPHERALID2) Field Descriptions ........18-24. POM Peripheral ID 3 Register (POMPERIPHERALID3) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 73 19-43. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions ........19-44. ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions ....19-45. ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) Field Descriptions SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 74 20-19. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions ..................20-20. Interrupt Offset Encoding Format ..........20-21. Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 75 20-68. HWAG Teeth Number Register (HWATHNB) Field Descriptions ......... 20-69. HWAG Current Teeth Number Register (HWATHVL) Field Descriptions ..............20-70. HWAG Filter Register (HWAFIL) Field Descriptions SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 76 ........21-21. Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions ........21-22. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 77 22-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions 1041 ..........22-20. GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions 1042 ............. 22-21. GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions 1042 SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 78 24-15. SPI Pin Control Register 2 (SPIPC2) Field Descriptions 1160 ............24-16. SPI Pin Control Register 3 (SPIPC3) Field Descriptions 1161 ............24-17. SPI Pin Control Register 4 (SPIPC4) Field Descriptions 1162 List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 79 25-7. Superfractional Bit Modulation for LIN Master Mode and Slave Mode 1253 .................... 25-8. Timeout Values in T Units 1260 ....................25-9. SCI/LIN Control Registers 1273 SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 80 26-8. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions 1348 ........26-9. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions 1349 ..............26-10. SCI Flags Register (SCIFLR) Field Descriptions 1351 List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 81 27-24. I2C Peripheral ID Register 2 (I2CPID2) Field Descriptions 1401 ............27-25. I2C DMA Control Register (I2CDMACR) Field Descriptions 1402 ............27-26. I2C Pin Function Register (I2CPFNC) Field Descriptions 1402 SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 82 1482 ..........28-37. MDIO User Access Register 1 (USERACCESS1) Field Descriptions 1483 ........28-38. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions 1484 List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 83 28-85. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions 1521 ....28-86. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions 1521 SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 84 29-45. Non-ISO Endpoint Interrupt Status Register (EPN_STAT) Field Descriptions 1581 ........29-46. Non-ISO DMA Interrupt Status Register (DMAN_STAT) Field Descriptions 1582 ......29-47. DMA Receive Channels Configuration Register (RXDMA_CFG) Field Descriptions 1583 List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 85 ..........31-7. RTP Global Control Register (RTPGLBCTRL) Field Descriptions 1714 ..................31-8. FIFO Corresponding Addresses 1716 .................. 31-9. Pins Used for Data Communication 1716 SPNU503C – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 86 32-5. EFC Error Status Register (EFCERRSTAT) Field Descriptions 1741 ..........32-6. EFC Self Test Cycles Register (EFCSTCY) Field Descriptions 1741 ..........32-7. EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions 1742 List of Tables SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 87: Preface

    Glossary TI Glossary — This glossary lists and explains terms, acronyms, and definitions. Related Documentation From Texas Instruments For product information, visit the Texas Instruments website at http://www.ti.com. SPNA106— Initialization of Hercules™ ARM Cortex -R4F Microcontrollers Application Report. ®...
  • Page 88 SPNU577— Safety Manual for RM48x Hercules™ ARM Safety Critical Microcontrollers User's Guide. A ® safety manual for the Texas Instruments Hercules safety critical microcontroller product family. The product family utilizes a common safety architecture that is implemented in multiple application focused products.

  • Page 89: Introduction

    Chapter 1 SPNU503C – March 2018 Introduction ........................... Topic Page ................. Designed for Safety Applications ..................... Family Description .................. Endianism Considerations SPNU503C – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 90: Designed For Safety Applications

    Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU. Introduction SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 91 With integrated safety features and a wide choice of communication and control peripherals, the RM48x is an ideal solution for high performance real time control applications with safety critical requirements. SPNU503C – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 92 USB_FUNC.RXDPI SPI4_SIMO USB_FUNC.SE0O EMIF_nRAS SPI4 SPI4_SOMI USB_FUNC.SUSPENDO EMIF_nCAS SPI4_nCS USB_FUNC.TXDO SPI4_nENA USB_FUNC.VBUSI MIBSPI5_CLK MIBSPI5_SIMO[3:0] MibSPI5 MIBSPI5_SOMI[5:0] MibADC1 MibADC2 N2HET1 N2HET2 MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX Introduction SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 93: Endianism Considerations

    /**lt; 0xF448: CS to Transmit char T2CDELAY /**lt; 0xF449: Transmit to CS char T2EDELAY /**lt; 0xF44A: Transmit to ENA char C2EDELAY /**lt; 0xF44B: CS to ENA SPNU503C – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 94: Architecture

    ........................... Topic Page ....................... Introduction ..................Memory Organization ....................... Exceptions ......................Clocks ............System and Peripheral Control Registers Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 95: Introduction

    Introduction www.ti.com Introduction The RM48x family of microcontrollers is based on the Texas Instruments TMS570 Architecture. This chapter describes specific aspects of the architecture as applicable to the RM48x family of microcontrollers. 2.1.1 Architecture Block Diagram The RM48x microcontrollers are based on the TMS570 Platform architecture, which defines the interconnect between the bus masters and the bus slaves.

  • Page 96: Definitions Of Terms

    General-purpose Input/Output The GIO module allows up to 16 terminals to be used as general-purpose Input or Output. Each of these are also capable of generating an interrupt to the CPU. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 97 This is the main device SCR. It arbitrates between the accesses from multiple Resource Controller bus masters to the bus slaves using a round robin priority scheme. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 98: Bus Master / Slave Access Privileges

    Not allowed Allowed Allowed Allowed Allowed EMAC User Not allowed Allowed Not allowed Allowed Not allowed OHCI User Not allowed Allowed Not allowed Allowed Not allowed Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 99: Memory Organization

    The device also supports the swapping of the CPU instruction memory (flash) and data memory (RAM). This can be done by configuring the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1). SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 100: Memory-Map Table

    0xF00C_0000 0xF00C_03FF 512B Flash Bank 0 TI OTP–ECC,TCM 0xF00C_0400 0xF00C_07FF 512B Flash Bank 1 TI OTP–ECC, 0xF00C_1C00 0xF00C_1FFF 512KB EEPROM Bank EEPROM Bank–ECC 0xF010_0000 0xF013_FFFF 256KB Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 101 0x800. Wrap around for accesses to unimplemented address MIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 102 Reads return zeros, DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B writes have no effect Reads return zeros, DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B writes have no effect Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 103 Reads return zeros, PPS5 0xFFFF_F700 0xFFFF_F7FF 256B 256B writes have no effect Reads return zeros, RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B writes have no effect SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 104: Flash Memory

    0x000E_0000 0x000F_FFFF 128K Bytes 0x0010_0000 0x0011_FFFF 128K Bytes 0x0012_0000 0x0013_FFFF 128K Bytes 0x0014_0000 0x0015_FFFF 128K Bytes 0x0016_0000 0x0017_FFFF Bank 1: 1.5M Bytes 128K Bytes 0x0018_0000 0x0019_FFFF Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 105 The ECC protection for accesses to the EEPROM emulation flash bank can be enabled by writing 0xA to the EDACEN field of the flash module’s Error Correction Control Register 1 (FEDACCTRL1). See Chapter 5 for more details. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 106: On-Chip Sram

    0 .. 1 MIBADC1 Dual-port Dual-port 0 .. 5 N2HET1 Dual-port 0 .. 11 HET TU1 Dual-port 0 .. 5 Dual-port 0 .. 8 MIBADC2 Dual-port Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 107 Single-port 6,21,22,25,27,28 0x0D300020 0x00000000 0xFFFFFFFF, 3,4,5,7,8,9,11,14,15,18,20, 0x00001000 pmos_open Dual-port 0x028A65DC 0x00000000 24,26 0xFFFFFFFF, 0x00002000 pmos_open Single-port 6,21,22,25,27,28 0x0D300020 0x00000000 0xFFFFFFFF, 0x00004000 pmos_open_slice1 Dual-port 10,12,13,19,23 0x00441A00 0x00000000 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 108 For HCLK = 180 MHz, VCLK = 90 MHz, PBIST ROM_CLK = 90 MHz, the March13 algorithm takes 14.02 ms to run on all on-chip SRAMs. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 109 DEV_MMIDONEn (where n = 31:0) (from memory modules to System module) Black indicates System register activity. Gray indicates inter-module activity, not accessible via System register. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 110 This is independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The MibSPIx modules need to be released from reset by writing 1 to their SPIGCR0 registers before starting auto-initialization on their respective RAMs. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 111: Exceptions

    An error occurring on an instruction fetch generates a prefetch abort. Errors occurring on data accesses generate data aborts. Aborts are also categorized as being either precise or imprecise. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 112 The A-bit in the CPSR is set by default. This means that no imprecise abort exception will occur. The application must enable imprecise abort exception generation by clearing the A- bit of the CPSR. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 113: System Software Interrupts

    This label is an 8-bit value that can then be used by the interrupt service routine to perform the required task based on the value provided. The source of the system software interrupt is reflected in the system software interrupt vector (SSIVEC) register. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 114: Clocks

    Chapter 10 for more information on enabling/disabling the oscillator and PLL. On the RM48x microcontrollers, the clock sources 0, 4, and 5 are enabled by default. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 115: Clock Domains

    • Divided down from HCLK VCLK3 OSCIN GHVSRC • Can be HCLK/1, HCLK/2,... or HCLK/16 • Is disabled separately from HCLK via the CDDISx registers bit 8 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 116 Each of the control registers indicated in Table 2-10 are defined in Section 2.5. The AC timing characteristics for each clock domain are specified in the device datasheet. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 117: Low Power Modes

    This section describes three particular low-power modes and their typical characteristics. They are not the only low-power modes configurable by the application, as just described. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 118 Refer to the individual module chapters for more information about the sequence to be followed to safely enter a low-power mode. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 119: Clock Test Mode

    PLL2 free-running clock output 0110 PLL2 Valid status 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 LF LPO Valid status 1001 RTI Base 1001 Reserved 1010 Reserved 1010 Reserved SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 120: Embedded Trace Macrocell (Etm-R4)

    Table 2-13. EXTCTL_Out_Port Register Field Descriptions Field Value Description 31-2 Reserved Reads return 0. Writes have no effect. EXTCTLOUT EXTCTL output control. Tied-zero VCLK ETMTRACECLKIN Tied-zero Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 121: Safety Considerations For Clocks

    Section 2.4.6.4.1 Section 2.4.6.4.2. This mechanism can be used to use a known-good clock to measure the frequency of another clock. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 122 As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference clock. The clock for counter 1 can be selected from among 2 options. See Chapter 11 for more details on the DCC usage. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 123: System And Peripheral Control Registers

    DFT Control Register Section 2.5.1.32 DFTCTRLREG2 DFT Control Register 2 Section 2.5.1.33 98h-9Ch Reserved Reserved GPREG1 General Purpose Register Section 2.5.1.34 IMPFASTS Imprecise Fault Status Register Section 2.5.1.35 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 124 Global Status Register Section 2.5.1.50 DEVID Device Identification Register Section 2.5.1.51 SSIVEC Software Interrupt Vector Register Section 2.5.1.52 SSIF System Software Interrupt Flag Register Section 2.5.1.53 Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 125 The ECLK pin is an output. Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 126 Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 127 Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 128 Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in input mode by setting the ECPCLKDIR bit to 0 in the SYSPC2 register. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 129 Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in input mode by setting the ECPCLKDIR bit to 0 in the SYSPC2 register. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 130 Clock Source 5 High Frequency LPO (Low Power Oscillator) clock Clock Source 6 PLL2 Clock Source 7 EXTCLKIN2 NOTE: Nonimplemented clock sources should not be enabled or used. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 131 CSDIS register (offset 30h), the CSDISSET register (offset 34h) and the CSDISCLR register (offset 38h). NOTE: A list of the available clock sources is shown in Table 2-29. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 132 CSDIS register (offset 30h), the CSDISSET register (offset 34h) and the CSDISCLR register (offset 38h). NOTE: A list of the available clock sources is shown in Table 2-29. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 133 VCLK2 domain off. The VCLK2 domain is enabled. The VCLK2 domain is disabled. VCLKPOFF VCLK_periph domain off. The VCLK_periph domain is enabled. The VCLK_periph domain is disabled. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 134 The HCLK and VCLK_sys domains are enabled. The HCLK and VCLK_sys domains are disabled. GCLKOFF GCLK domain off. The GCLK domain is enabled. The GCLK domain is disabled. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 135 Read: The VCLK2 domain is enabled. Write: The VCLK2 domain is unchanged. Read: The VCLK2 domain is disabled. Write: The VCLK2 domain is set to the enabled state. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 136 Read: The VCLKA[4-3] domain is disabled. Write: The VCLKA[4-3] domain is cleared to the enabled state. Reserved Reads return 0 or 1 and privilege mode writes allowed. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 137 Read: The GCLK domain is enabled. Write: The GCLK domain is unchanged. Read: The GCLK domain is disabled. Write: The GCLK domain is cleared to the enabled state. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 138 Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2. Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2. Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2. 8h-Fh Reserved Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 139 VCLK is the source for peripheral asynchronous clock1. NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock sources is shown in Table 2-29. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 140 Clock source7 is the source for RTICLK1. 8h-Fh VCLK is the source for RTICLK1. NOTE: A list of the available clock sources is shown in Table 2-29. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 141 Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is not fully stable), the respective clock domain is disabled. NOTE: A list of the available clock sources is shown in Table 2-29. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 142 Note: It is recommended that a value of 0101b be used to disable the memory self-test controller. This value will give maximum protection from a bit flip inducing event that would inadvertently enable the controller. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 143 Note: It is recommended that a value of 5h be used to disable memory hardware initialization. This value will give maximum protection from an event that would inadvertently enable the controller. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 144 Note: Software should ensure that both the memory self-test global enable key (MSTGENA) and the memory hardware initialization global key (MINITGENA) are not enabled at the same time. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 145 Read: Memory self-test is not completed. Write: A write of 0 has no effect. Read: Memory self-test is completed. Write: The bit is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 146 Reserved REFCLKDIV R/WP-0 R/WP-2h PLLMUL R/WP-5F00h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 147 100h VCO CLK INT CLK 5B00h x 92 VCO CLK INT CLK 5C00h x 93 VCO CLK INT CLK FF00h x 256 VCO CLK INT CLK SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 148 If frequency modulation is disabled and SPR_AMOUNT is changed, there is no effect on the PLL output clock. NV = 1/2048 NV = 2/2048 1FFh NV = 512/2048 Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 149 ECPCLK slew control. This bit controls between the fast or slow slew mode. Fast mode is enabled; the normal output buffer is used for this pin. Slow mode is enabled; slew rate control is used for this pin. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 150 NOTE: Die Identification Information The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 151 Read: OSC freq is > 20MHz and ≤ 80MHz Write: A write of 1 has no effect. 15-13 Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 152 100.00% Default at Reset. 104.09 108.17 112.32 116.41 120.67 124.42 128.38 132.24 136.15 140.15 143.94 148.02 151.80x 155.50x 159.35% Reserved Reads return 0. Writes have no effect. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 153 65.78 70.75 75.63 80.61 85.39 90.23 95.11 100.00% Default at Reset 104.84 109.51 114.31 119.01 123.75 128.62 133.31 138.03 142.75 147.32 152.02 156.63 161.38 165.90 170.42 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 154 ECPCLKFUN bit to 1 in the SYSPC1 register. Clock going to ECLK pin is enabled. Others Clock going to ECLK pin is disabled. 15-12 Reserved Reads return 0. Writes have no effect. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 155 High-frequency LPO (Low-Power Oscillator) clock PLL2 clock output EXTCLKIN2 GCLK RTI Base Reserved VCLKA1 Reserved VCLKA3 VCLKA4 Reserved NOTE: Nonimplemented clock sources should not be enabled or used. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 156 Register key enable. All the bits can be written to only when the key is enabled. On reset, these bits will be set to 5h. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 157 Register key disable. All bits in this register will maintain their default value and cannot be (except Ah) written. Register key enable. All the bits can be written to only when the key is enabled. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 158 FBSLIP filtering is enabled. Recommended to program Ah in this bit values field. Enabling of the FBSLIP occurs when the KEY is programmed and a non-zero value is present in the COUNT field. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 159 RTP Enable EMI mode for each connected output buffers. 1h-FFFEh Enable/Disable EMI mode for connected output buffers. FFFFh Disable EMI mode for each connected output buffer. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 160 The peripheral frame did not generate the last imprecise abort. The peripheral frame was written with an illegal address and generated an imprecise abort. Reserved Reads return 0. Writes have no effect. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 161 Note: These bits are only updated when an imprecise abort occurs. Note: These bits are cleared to 0 only on power-on reset. The value of this register remains unchanged after all other resets. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 162 SSKEY2 field matches the key (84h); therefore, byte writes cannot be performed on the SSDATA2 field. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 163 SSKEY4 field matches the key (A2h); therefore, byte writes cannot be performed on the SSDATA4 field. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 164 There are no wait states for eSRAM during the data phase. The eSRAM data phase setup time is increased by one HCLK cycle. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 165 0. Program memory (Flash) starts at address 800 0000h. Default memory-map: Program memory (Flash) starts at address 0. eSRAM starts at address 800 0000h. All other values The device memory-map is unchanged. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 166 Reads return 0. Writes have no effect. CPU RESET CPU Reset. Only the CPU is reset whenever this bit is toggled. There is no system reset. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 167 Peripheral enable bit. The application must set this bit before accessing any peripheral. The global peripheral/peripheral memory frames are in reset. All peripheral/peripheral memory frames are out of reset. Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 168 VBUS clock or OSCIN as shown in the formula: V C L K O S C I N E C L K E C P D I V Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 169 Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. No reset will occur. 0, 2h-3h A global system reset will occur. 13-0 Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 170 Note: A software system reset can be initiated by writing to the RESET bits in the SYSECR register. No software reset has occurred. A software reset occurred. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 171 JTAG data register. In either case, the autoload machine was not able or not allowed to complete its operation. Others Read: Reserved. Write: These bits are cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 172 Read: No oscillator failure has been detected. Write: The bit is unchanged. Read: An oscillator failure has been detected. Write: The bit is cleared to 0. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 173 0-1Fh Version. These bits provide the revision of the device. PLATFORM ID The device is part of the TMS570 family. The TMS570 ID is always 5h. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 174 A software interrupt has been generated by writing the correct key value to The SSIR3 register. A software interrupt has been generated by writing the correct key value to The SSIR4 register. 5h-FFh Reserved Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 175 Read: No IRQ/FIQ interrupt was generated since the bit was last cleared. Write: The bit is unchanged. Read: An IRQ/FIQ interrupt was generated. Write: The bit is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 176: Secondary System Control Registers (Sys2)

    Die Identification Register Lower Word Section 2.5.2.9 DIEIDH_REG3 Die Identification Register Upper Word Section 2.5.2.10 NOTE: All additional registers in the secondary system frame are reserved. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 177 User and privileged mode (read): Privileged mode (write): 100h VCOCLK2 INTCLK2 5B00h x 92 VCOCLK2 INTCLK2 5C00h x 93 VCOCLK2 INTCLK2 FF00h x 256 VCOCLK2 INTCLK2 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 178 Reserved Reads return 0. Writes have no effect. VCLK3R VBUS clock3 ratio. The ratio is HCLK divide by 1. The ratio is HCLK divided by 16. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 179 VCLK or a divided VCLK is the source for peripheral asynchronous clock4. See the device- specific data manual for details. 15-11 Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 180 VCLK is the source for peripheral asynchronous clock3. NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock sources is shown in Table 2-29. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 181 PLL RFSLIP filtering is enabled. Recommended to program Ah in this bit field. Enabling of the PLL RFSLIP occurs when the KEY is programmed and a non- zero value is present in the COUNT field. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 182 NOTE: Die Identification Information The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 183 Value Description 31-0 DIEIDL2(95-64) 0-FFFF FFFFh This read-only register contains the lower word (95:64) of the die ID information. The contents of this register is reserved. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 184 Value Description 31-0 DIEIDH2(127-96) 0-FFFF FFFFh This read-only register contains the upper word (127:97) of the die ID information. The contents of this register is reserved. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 185: Peripheral Central Resource (Pcr) Control Registers

    Section 2.5.3.21 PSPWRDWNCLR1 Peripheral Power-Down Clear Register 1 Section 2.5.3.22 PSPWRDWNCLR2 Peripheral Power-Down Clear Register 2 Section 2.5.3.23 PSPWRDWNCLR3 Peripheral Power-Down Clear Register 3 Section 2.5.3.24 SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 186 Read: The peripheral memory framen can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 187 Read: The peripheral memory framen can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 188 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is set to 1. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 189 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is set to 1. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 190 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is cleared to 0. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 191 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 192 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers is cleared to 0. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 193 Write: The bit is unchanged. Read: The peripheral memory clock[63-32] is inactive. Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers is set to 1. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 194 Write: The bit is unchanged. Read: The peripheral memory clock[63-32] is inactive. Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers is cleared to 0. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 195 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is set to 1. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 196 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is set to 1. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 197 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 198 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is cleared to 0. Architecture SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 199 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is cleared to 0. SPNU503C – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 200: Power Management Module (Pmm)

    Power Management Module (PMM) This chapter describes the power management module (PMM)..........................Topic Page ......................Overview ....................Power Domains ....................PMM Operation ....................PMM Registers Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 201: Overview

    Overview The microcontroller is part of the Hercules family of microcontrollers from Texas Instruments for safety- critical applications. Several functions are implemented on this microcontroller targeted towards varied applications. The core logic is divided into several domains that can be independently turned on or off based on the application’s requirements.

  • Page 202: Power Domains

    ON or OFF one time during device initialization. Once configured, it is not allowed to change the state of a power domain without first asserting a system reset. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 203 SPI4 SPI4_SOMI USB_FUNC.SUSPENDO EMIF_nCAS SPI4_nCS USB_FUNC.TXDO EMIF_RnW SPI4_nENA USB_FUNC.VBUSI MIBSPI5_CLK MIBSPI5_SIMO[3:0] MibSPI5 MIBSPI5_SOMI[5:0] MibADC1 MibADC2 N2HET1 N2HET2 MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 204: Pmm Operation

    1. Write the correct key to the MEMPDONx register to power down the domain. 2. Poll for MEMPDPWRSTATx.MEMPDPWR_STATx to become “00”. The power domain is now powered down. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 205: Reset Management

    PSCON compare error. This error signal is mapped to the Error Signaling Module’s (ESM) Group1 channel 38. The application can define the response to this error. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 206 No status flags are updated in this mode. Normal operation of the compare block is resumed once the CPU exits the debug mode. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 207 Memory PD PSCON Diagnostic Compare Status Register 1 Section 3.4.18 MPDDCSTAT2 Memory PD PSCON Diagnostic Compare Status Register 2 Section 3.4.19 ISODIAGSTAT Isolation Diagnostic Status Register Section 3.4.20 SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 208 Reserved Any other value Read: Power domain PD5 is in Active state. Write: Power domain PD5 is commanded to switch to Active state. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 209 Read: Power domain RAM_PD3 is in Active state. Write: Power domain RAM_PD3 is commanded to switch to Active state. Reserved Read returns 0. Writes have no effect. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 210 Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged Mode only. Enable clocks to logic power domain PD2. Disable clocks to logic power domain PD2. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 211 Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. Write in Privileged Mode only. No effect to state of clocks to power domain PD2. Disable clocks to logic power domain PD2. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 212 Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged Mode only. No effect to state of clocks to power domain PD2. Enable clocks to logic power domain PD2. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 213 Logic power domain PD2 is switched OFF. Logic power domain PD2 is in the Idle state. Reserved Logic power domain PD2 is in the Active state. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 214 Logic power domain PD3 is switched OFF. Logic power domain PD3 is in the Idle state. Reserved Logic power domain PD3 is in the Active state. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 215 Logic power domain PD4 is switched OFF. Logic power domain PD4 is in the Idle state. Reserved Logic power domain PD4 is in the Active state. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 216 Logic power domain PD5 is switched OFF. Logic power domain PD5 is in the Idle state. Reserved Logic power domain PD5 is in the Active state. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 217 Read in User and Privileged Mode. Memory power domain RAM_PD1 is switched OFF. Reserved Reserved Memory power domain RAM_PD1 is in the Active state. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 218 Read in User and Privileged Mode. Memory power domain RAM_PD2 is switched OFF. Reserved Reserved Memory power domain RAM_PD2 is in the Active state. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 219 Read in User and Privileged Mode. Memory power domain RAM_PD3 is switched OFF. Reserved Reserved Memory power domain RAM_PD3 is in the Active state. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 220 Disable automatic clock wake up. The application must enable clocks by clearing the correct bit in the PDCLK_DIS register. Enable automatic clock wake up when a power domain transitions to Active state. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 221 Read in User and Privileged mode returns the current value of MKEY. Write in Privileged mode only. Lock Step mode Self-test mode Error Forcing mode Self-test Error Forcing Mode All others Lock Step mode SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 222 Bit 0 for PD2. Read in User and Privileged Mode. Writes have no effect. Self-test is ongoing if self-test mode is entered. Self-test is complete. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 223 Bit 2 for PD4, Bit 1 for PD3, Bit 0 for PD2. Read in User and Privileged Mode. Writes have no effect. Self-test passed. Self-test failed. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 224 Bit 0 for RAM_PD1. Read in User and Privileged Mode. Writes have no effect. Self-test is ongoing if self-test mode is entered. Self-test is complete. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 225 Bit 2 for RAM_PD3, Bit 1 for RAM_PD2, Bit 0 for RAM_PD1. Read in User and Privileged Mode. Writes have no effect. Self-test passed. Self-test failed. SPNU503C – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 226 Read in User and Privileged Mode. Writes have no effect. Isolation is enabled for corresponding power domain. Isolation is disabled for corresponding power domain. Power Management Module (PMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 227: Spnu503C - March 2018

    Main Features of I/O Multiplexing Module (IOMM) ............... Control of Multiplexed Functions ....................Safety Features ....................IOMM Registers ................. Signal Multiplexing and Control SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 228 Buffer Enable) and LPM (Low Power Mode). Each of these signals is an output of a multiplexor which allows the selected function to control all available features of the output buffer. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 229 Input Pin # Input Pin # SPI4SIMO – PINMMR5[9] PINMMR23[16] SPI4SOMI – PINMMR5[17] PINMMR23[24] SPI4CLK – PINMMR5[1] PINMMR23[8] SPI4NENA – PINMMR4[17] PINMMR24[0] SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 230 GIO signal toggle can trigger an interrupt request, when the application actually is using the function multiplexed with this GIO signal. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 231 CPU when the external fault monitor circuitry drives the MibSPI3_nCS[0] / AD2EVT terminal low to indicate a fault condition to the N2HET2 module. SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 232 Protection Error – occurs when the CPU writes to an IOMM register while not in a privileged mode of operation. The application can read the Error Raw Status register (Section 4.5.5) to determine the actual cause of the error. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 233 E84h Module Id 15-11 REV RTL RTL Revision 10-8 REV MAJOR Major Revision REV CUSTOM Custom Revision REV MINOR Minor Revision SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 234 Reads return zeros, writes have no effect. ENDIAN Device endianness Device is configured in little-endian mode. Device is configured in big-endian mode. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 235 Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to the PINMMRnn registers. SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 236 Read: Protection Error has not occurred. Write: Writing 0 has no effect. Read: Protection Error has been detected. Write: Protection Error status is set. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 237 Read: Protection Error Signaling is disabled. Write: Writing 0 has no effect. Read: Protection Error Signaling is enabled. Write: Protection Error status is cleared. SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 238 Read: Protection Error Signaling is disabled. Write: Writing 0 has no effect. Read: Protection Error Signaling is enabled. Write: Protection Error Signaling is enabled. I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 239 Read returns zeros, writes have no effect. FAULT_ADDR Fault Address. The fault address offset in case of an address error or a protection error condition. SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 240 Type of fault detected No fault User execute fault User write fault User read fault Supervisor execute fault Supervisor write fault Supervisor read fault I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 241 Each of these byte-fields control the functionality on a given ball/pin. Please refer to Table 4-16 for a list of multiplexed signals sorted by the control registers. 23-16 PINMMRx[23-16] 15-8 PINMMRx[15-8] PINMMRx[7-0] SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 242 FFFF EB2Ch N2HET1[06] PINMMR7[16] SCIRX PINMMR7[17] RESERVED PINMMR7[18] RESERVED PINMMR7[19] RESERVED PINMMR7[20] ETMDATA[30] PINMMR7[24] EMIF_DATA[14] PINMMR7[25] RESERVED PINMMR7[26] RESERVED PINMMR7[27] RESERVED PINMMR7[28] I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 243 FFFF EB50h EMIF_ADDR[16] PINMMR16[16] RTP_DATA[02] PINMMR16[17] RESERVED PINMMR16[18] RESERVED PINMMR16[19] RESERVED PINMMR16[20] ETMDATA[13] PINMMR16[24] EMIF_nOE PINMMR16[25] RESERVED PINMMR16[26] RESERVED PINMMR16[27] RESERVED PINMMR16[28] SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 244 FFFF EB74h N2HET1[25] PINMMR25[16] RESERVED PINMMR25[17] RESERVED PINMMR25[18] RESERVED PINMMR25[19] RESERVED PINMMR25[20] N2HET1[27] PINMMR25[24] RESERVED PINMMR25[25] RESERVED PINMMR25[26] RESERVED PINMMR25[27] RESERVED PINMMR25[28] I/O Multiplexing and Control Module (IOMM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 245 FFFF EB88h RESERVED PINMMR30[16] RESERVED PINMMR30[17] RESERVED PINMMR30[18] RESERVED PINMMR30[19] RESERVED PINMMR30[20] RESERVED PINMMR30[24] RESERVED PINMMR30[25] RESERVED PINMMR30[26] RESERVED PINMMR30[27] RESERVED PINMMR30[28] SPNU503C – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 246 ......................SECDED ....................Memory Map ..........Power On, Power Off, and Reset Considerations ..............Emulation and SIL3 Diagnostic Modes .................... Control Registers F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 247 Refer to the following documents for support in how to initialize and use the on-chip Flash and its API: • Initialization of Hercules ARM Cortex-R4F Microcontrollers Application Report (SPNA106) • F021 (Texas Instruments 65nm Flash) Flash API Reference Guide (SPNU501) 5.1.1 Features • Read, program and erase with a single 3.3 V supply voltage •...
  • Page 248 Read Margin 0 mode: More stringent read mode designed for early detection of marginally programmed bits. 5.1.3 F021 Flash Tools Texas Instruments provides the following tools for F021 Flash: • nowECC Generation Tool - to generate the Flash ECC from the Flash data.
  • Page 249 EEPROM Emulation Flash. It is only necessary to initialize the ECC values of the locations which will be intentionally read by the CPU or other bus masters. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 250 For Odd parity, XOR a 1 to the row’s XOR result. For even Parity, use the row’s XOR result directly. Each ECC[x] bit represents the XOR of all the address and data bits marked with x in the same row. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 251 0 0 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 Bit[0] SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 252 Dxx - Single-bit data error, correctable • Axx - Single-bit address error, uncorrectable • D - Double-bit error, uncorrectable • M - Multi-bit errors, uncorrectable F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 253 0x00000008 64 – bit data word 1 ECC2 ECC3 ECC0 0x00000000 64 – bit data word 0 0xF0400000 ECC0 ECC1 0xF0400000 ECC1 SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 254 Table 5-5. TI OTP Sector Information Address Bank TI OTP Address F008 0158h F008 2158h F008 4158h F008 6158h F008 8158h F008 A158h F008 C158h F008 E158h F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 255 Table 5-7. TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions Field Description 31-24 HFLPO_TRIM HF LPO Trim Solution 23-16 LFLPO_TRIM LF LPO Trim Solution 15-0 MAX_HCLK Maximum HCLK Speed SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 256 F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 257 ECC Malfunction test mode 1 (same data) ECC Malfunction test mode 2 (inverted data) Address Tag Register test mode Reserved ECC Data Correction Diagnostic test mode SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 258 NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test values are written, the DIAG_TRIG should then be set high to validate the diagnostic result. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 259 =(3 or 4) (Diag_Mode=3 or 4) and Diag_Trig) Raw ECC Diag_Mode=0 = 0? ¹ register Diag En key 0101 Zero means no correction FRAW_ECC SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 260 NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test values are written, the DIAG_TRIG should then be set high to validate the diagnostic result. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 261 10. Put 2h in PAR_OVR_KEY field (00005400h) of the FPAR_OVR register to clear DAT_INV_PAR field. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 262 FRAW_DATAL D_UNC_ERR FRAW_ECC FRAW_ECC FUNC_ERR_ADD FRAW_DATAH EE_CME FRAW_DATAL EE_D_UNC_ERR FRAW_ECC EE_UNC_ERR_ADD Register output value will change, but will not contain useful information. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 263 This section details the Flash module registers, summarized in Table 5-12. A detailed description of each register and its bits is also provided. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 264 Section 5.7.40 FFF8 7320h EE_UNC_ERR_ADD EEPROM Emulation Uncorrectable Error Address Register Section 5.7.41 FFF8 7400h FCFG_BANK Flash Bank Configuration Register Section 5.7.42 F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 265 Reserved Reads return 0. Writes have no effect. ENPIPE Enable Pipeline Mode Pipeline mode is disabled. Pipeline mode is enabled. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 266 Note: Reading ECC bits will generate an ECC error based on the contents of the 8 ECC bits and the 64 data bits they protect. 15-11 Reserved Reads return 0. Writes have no effect. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 267 OTP will be prevented. All Other Values Error Detection and Correction events are captured and sent to the ESM. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 268 This register only increments when profiling mode is enabled. This register is not affected by the EOFEN or EZEFEN error control bits in the FEDACCTRL1 register. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 269 ECC location associated with the failure. When reading an ECC byte, the ECC is checked against the 64 data bits they protect. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 270 The error was one of the 64 data bits. The error was one of the 8 check bits. ERR_POS The bit address of the single-bit error. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 271 SECDED malfunction is not detected on Bus 2. SECDED malfunction is detected on Bus 2. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 272 This bit sets when diagnostic mode 1 discovers a single-bit correctable error using the ECC. Multi-bit errors are flagged using the D_UNC_ERR bit. The uncorrectable error address must be unfrozen in order to set this bit. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 273 SEC_THRESHOLD register. Error profiling is enabled and the number of correctable errors has reached the threshold programmed into the SEC_THRESHOLD register. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 274: Flash Uncorrectable Error Address Register (Func_Err_Add) [Offset = 20H]

    ECC location associated with the failure. When reading an ECC byte, the ECC is checked against the 64 data bits they protect. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 275: Flash Error Detection And Correction Sector Disable Register (Fedacsdis) [Offset = 24H]

    If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 0. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 276: Primary Address Tag Register (Fprim_Add_Tag) [Offset = 28H]

    DIAG_MODE is 0 or 7h. Valid reads can occur in any mode. The register will clear when an address tag error is found and when leaving DIAG_MODE 5. Always 0000 F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 277: Flash Bank Protection Register (Fbprot) [Offset = 30H]

    The corresponding numbered sector is disabled for program or erase access. The corresponding numbered sector is enabled for program or erase access. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 278: Flash Bank Busy Register (Fbbusy) [Offset = 38H]

    The corresponding bank is not busy. The corresponding bank is busy with a state machine or bus 2 operation, or the bank is not implemented. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 279: Flash Bank Access Control Register (Fbac) [Offset = 3Ch]

    Note: There is not a programmable Bank Sleep counter and Standby counter register. The number of clock cycles to transition from sleep to standby and standby to active is hardcoded in the Flash wrapper design. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 280: Flash Bank Fallback Power Register (Fbfallback) [Offset = 40H]

    Bank standby mode Reserved Bank active mode BANKPWR0 Bank 0 Fallback Power Mode Bank sleep mode Bank standby mode Reserved Bank active mode F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 281: Flash Bank/Pump Ready Register (Fbprdy) [Offset = 44H]

    Flash bank is in the sleep or standby state. Flash bank is in the active state, or the bank is not implemented. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 282: Flash Pump Access Control Register 1 (Fpac1) [Offset = 48H]

    Reads return 0. Writes have no effect. PUMPPWR Flash Charge Pump Fallback Power Mode Sleep (all pump circuits disabled). Active (all pump circuits active). F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 283: Flash Pump Access Control Register 2 (Fpac2) [Offset = 4Ch]

    BANK[2:0] and read back the value to see if what was written can be read back. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 284: Flash Module Status Register (Fmstat) [Offset = 54H]

    When set, this bit indicates that the user attempted to program a 1 where a 0 was already present. This bit is cleared by the Clear Status command. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 285 1s. A SLOCK error will occur if attempting to do a sector erase with either BSE is cleared or SECT_ERASED is set. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 286: Eeprom Emulation Data Msw Register (Femu_Dmsw) [Offset = 58H]

    This register is also used in diagnostic modes 1 and 2 where it supplies the lower data for checking the SECDED hardware. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 287: Eeprom Emulation Ecc Register (Femu_Ecc) [Offset = 60H]

    SECDED selected by DIAG_ECC_SEL. This register is only available when the module is configured to use the ECC logic; otherwise, it is a reserved register. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 288: Eeprom Emulation Address Register (Femu_Addr) [Offset = 68H]

    Reserved. Writes have no effect. The lower three bits of the CPU address are not used in the ECC calculation to align the data on a 64-bit boundary. These bits will read back as 0. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 289: Diagnostic Control Register (Fdiagctrl) [Offset = 6Ch]

    Select BUS2 SECDED for diagnostic testing. Select FEE SECDED for diagnostic testing (Same ECC logic as BUS2 but sets FEE registers). 6h-7h Reserved 11-10 Reserved Reserved SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 290 ECC Malfunction test mode 2 (inverted data) (see Section 5.6.2.4 Address Tag Register test mode (see Section 5.6.2.5 Reserved ECC Data Correction Diagnostic test mode (see Section 5.6.2.6 F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 291: Uncorrected Raw Data High Register (Fraw_Datah) [Offset = 70H]

    1 through 6 with DIAG_EN_KEY=0101. These modes must be set for at least one clock cycle before writing to any FRAW* register. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 292: Uncorrected Raw Ecc Register (Fraw_Ecc) [Offset = 78H]

    DIAG_EN_KEY=0101. This mode must be set for at least one clock cycle before writing to any FRAW* register. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 293: Parity Override Register (Fpar_Ovr) [Offset = 7Ch]

    In diagnostic mode 7 the FPAR_OVR should be set to 00005Axxh to allow writes to the DAT_INV_PAR field. This field should be written before entering diagnostic mode 7. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 294: Flash Error Detection And Correction Sector Disable Register (Fedacsdis2) [Offset = C0H]

    If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 2. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 295: Fsm Register Write Enable (Fsm_Wr_Ena) [Offset = 288H]

    Each sector will not be erased. 15-0 Reserved These bits are used by the state machine during bank erase. Do not write to these bits. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 296: Eeprom Emulation Configuration Register (Eeprom_Config) [Offset = 2B8H]

    2 will wait for 32 periods after the last access. Each access will reset the counter to the AUTOSTART_GRACE value × 16. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 297: Eeprom Emulation Error Detection And Correction Control Register 1 (Ee_Ctrl1) [Offset = 308H]

    EE_CTRL2 register. Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 298 Note: It is recommended to leave the EE_EDACEN field as 1010 to guard against soft errors from flipping the EE_EDACEN to a disabled state. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 299: Eeprom Emulation Error Correction And Correction Control Register 2 (Ee_Ctrl2) [Offset = 30Ch]

    This register is not affected by the EE_ZERO_EN or EE_ONE_EN error control bits in the EE_CTRL1 register. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 300: Eeprom Emulation Correctable Error Address Register (Ee_Cor_Err_Add) [Offset = 314H]

    ECC location associated with the failure. When reading an ECC byte, the ECC is checked against the 64 data bits they protect. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 301: Eeprom Emulation Correctable Error Position Register (Ee_Cor_Err_Pos) [Offset = 318H]

    The error was one of the 64 data bits. The error was one of the 8 check bits. EE_ERR_POS 0-FFh The bit address of the single-bit error. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 302: Eeprom Emulation Error Status Register (Ee_Status) [Offset = 31Ch]

    EEPROM Emulation Compare Malfunction Error Compare malfunction was not detected on the Bus2 SECDED logic. Compare malfunction was detected on the Bus2 SECDED logic. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 303: Eeprom Emulation Uncorrectable Error Address Register (Ee_Unc_Err_Add) [Offset = 320H]

    ECC location associated with the failure. When reading an ECC byte, the ECC is checked against the 64 data bits they protect. SPNU503C – March 2018 F021 Flash Module Controller (FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 304: Flash Bank Configuration Register (Fcfg_Bank) [Offset = 400H]

    This read-only value indicates the maximum number of bits that can be programmed in the bank in one operation. The 144 bits includes 128 data bits and 16 ECC bits. Reserved Writes have no effect. F021 Flash Module Controller (FMC) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 305 RAM Memory Map ....................Safety Features .................. TCRAM Auto-Initialization ..................Trace Module Support ..............Emulation / Debug Mode Behavior ................Control and Status Registers SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 306: Tcram Module Connections

    – Support for Cortex-R4F CPU's Parity Protection Logic for BTCM Address Bus and Control Signals • Uses the CPU's TCM Address Parity Scheme and indicates an address bus parity error to the Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 307: Ram Memory Map

    ECC is also written. This can be done by setting the bit 1: BTCMRMW of c15, the Secondary Auxiliary Control Register of the CPU. This bit is already set by default. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 308 Control Register (PMNC) in the CPU. The TCRAM interface module can only capture the single-bit or double-bit ECC error occurrences once the CPU's event signaling mechanism is enabled. Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 309 MMI_INIT pulse from the system module. All enabled RAM data memory locations are initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 310 TCRAM Module Test Mode Vector Register Section 6.7.9 RAMPERADDR TCRAM Module Parity Error Address Register Section 6.7.10 INIT_DOMAIN Auto-Memory Initialization Enable Register Section 6.7.11 Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 311: Tcram Module Control Register (Ramctrl) [Offset = 00H]

    Note: Reads are allowed from the ECC memory regardless of the state of the ECC_WR_EN bit. ECC memory writes are disabled. ECC memory writes are enabled. Reserved Read returns 0. Writes have no effect. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 312: Tcram Module Single-Bit Error Correction Threshold Register (Ramthreshold) [Offset = 04H]

    1 then all single-bit error addresses are captured. To enable the error occurrence detection, the threshold must be set to a non-zero value. Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 313: Tcram Module Single-Bit Error Occurrences Counter Register (Ramoccur) [Offset = 08H]

    The SERR status flag in the RAMERRSTATUS register gets set regardless of whether the SERR interrupt is enabled or not. Single-bit error generation is disabled. Single-bit error generation is enabled. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 314: Tcram Module Error Status Register (Ramerrstatus) [Offset = 10H]

    This bit is set even if the single-bit error threshold interrupt is disabled. This bit must be cleared by writing 1 to it in order to clear the interrupt request and to enable subsequent single-bit error interrupt generation. Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 315: Tcram Module Single-Bit Error Address Register (Ramserraddr) [Offset = 14H]

    This register can only be reset by asserting power-on reset, and holds the last error address even after a system reset. Reserved Read returns 0. Writes have no effect. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 316: Tcram Module Uncorrectable Error Address Register (Ramuerraddr) [Offset = 1Ch]

    This register can only be reset by asserting power-on reset, and holds the last error address even after a system reset. Reserved Read returns 0. Writes have no effect. Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 317: Tcram Module Test Mode Control Register (Ramtest) [Offset = 30H]

    If there is a silicon malfunction on any of the comparator bits, then, ADDR_COMP_LOGIC_FAIL and ADDR_DEC_FAIL will be set, no UERRADDRESS is captured. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 318: Tcram Module Test Mode Vector Register (Ramaddrdecvect) [Offset = 38H]

    This is a 64-bit-aligned address is stored as an offset from the base of the TCRAM or ECC memory. Reserved Read returns 0. Writes have no effect. Tightly-Coupled RAM (TCRAM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 319: Auto-Memory Initialization Enable Register (Init_Domain) [Offset = 40H]

    5. bit[6] represents the enable bit for power domain 6. bit[7] represents the enable bit for power domain 7. SPNU503C – March 2018 Tightly-Coupled RAM (TCRAM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 320 RAM Grouping and Algorithm ..................... PBIST Flow ............ Memory Test Algorithms on the On-chip ROM ................... PBIST Control Registers ................PBIST Configuration Example Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 321: Pbist Block Diagram

    Figure 7-1. PBIST Block Diagram Host CPU Control Interface Memory Configurations, PBIST PBIST Controller Algorithms, System Backgrouns Memory Data Peripheral Path Memories Data Logger SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 322 RAM groups with the background patterns used for the particular algorithm. NOTE: March13 is the most recommended algorithm for the memory self-test. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 323: Pbist Memory Self-Test Flow Diagram

    Disable pbist clocks and ROM clock by writing PACT = 0 Disable PBIST Test by writing MSTGCR = 0x05 PBIST Selftest Done SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 324 NOTE: The contents of the selected memory before the test will be completely lost. User software must take care of data backup if required. Typically the PBIST tests are carried out at the beginning of Application software. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 325 – High voltage should operate better than low voltage. – Likewise, low temperature should operate better than high temperature. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 326 – Invert the data pattern for the above two steps to perform another sequence of aggressive writes. 5. DTXN2a: This algorithm is used to target the global column decode Logic. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 327 ROM Algorithm Mask Register Section 7.5.11 1C8h RINFOL RAM Info Mask Lower Register Section 7.5.12 1CCh RINFOU RAM Info Mask Upper Register Section 7.5.13 SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 328: Ram Configuration Register (Ramt) [Offset = 0160H]

    RDS values for each memory. 15-8 Data Width Register Sense Margin Select Register Pipeline Latency Select RAM Latency Select Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 329: Datalogger Register (Dlr) [Offset = 0164H]

    • DLR4: Config access mode This mode, when set, indicates the CPU is being used to access PBIST. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 330: Pbist Activate/Rom Clock Enable Register (Pact) [Offset = 0180H]

    As long as this bit is 0, any access to the PBIST will not go through and the PBIST will remain in an almost zero-power mode. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 331: Pbist Id Register [Offset = 184H]

    Reads return 0. Writes have no effect. PBIST ID This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 332: Override Register (Over) [Offset = 0188H]

    2. Only memories that are valid for all algorithms enabled via the ALGO register are selected. If the above two requirements are not met, the memory self-test will fail. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 333: Fail Status Fail Register 0 (Fsrf0) [Offset = 0190H]

    Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in system module. No failure occurred. Failure occurred on port 0. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 334: Fail Status Count 0 Register (Fsrc0) [Offset = 0198H]

    31-8 Reserved Reads return 0. Writes have no effect. FSRC1 Fail Status Count 1. Indicates the number of failures on port 1. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 335: Fail Status Address 0 Register (Fsra0) [Offset = 01A0H]

    31-16 Reserved Reads return 0. Writes have no effect. 15-0 FSRA1 Fail Status Address 1. Contains the address of the first failure. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 336: Fail Status Data Register 0 (Fsrdl0) [Offset = 01A8H]

    LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-13. Fail Status Data Register 1 (FSRDL1) Field Descriptions Field Description 31-0 FSRDL1 Failure data on port 1 Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 337: Rom Mask Register (Rom) [Offset = 01C0H]

    Selects algorithm 31 for PBIST run. Algorithm 1 is not selected. Selects algorithm 1 for PBIST run. 31-0 None of the algorithms are selected. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 338: Ram Info Mask Lower Register (Rinfol) [Offset = 01C8H]

    Selects RAM Group 1 for PBIST run. 31-0 None of the RAM Groups 1 to 32 are selected. NOTE: Please refer to Table 2-5 for RAM info groups. Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 339: Ram Info Mask Upper Register (Rinfou) [Offset = 01Cch]

    RAM Group 33 is not selected. Selects RAM Group 33 for PBIST run. 31-0 None of RAM Groups 33 to 64 are selected. SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 340 In case there is no failure (FSRF0 = 0x00), the memory self-test is completed: i. Disable the PBIST internal clocks. PACT = 0 ii. Disable the PBIST self-test. MSTGCR[3:0] = 0x5 Programmable Built-In Self-Test (PBIST) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 341 In case there is no failure (FSRF0 = 0x00), the memory self-test is completed: i. Disable the PBIST internal clocks. PACT = 0 ii. Disable the PBIST self-test. MSTGCR[3:0] = 0x5 SPNU503C – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 342 Page ..................General Description ................. Application Self-Test Flow ................ STC Test Coverage and Duration ..................STC Control Registers ................STC Configuration Example CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 343 Peripheral Bus (VBUSP) Interface. This block controls the reseeding (reloading the existing seed of the PRPG) in the LBIST controller. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 344: Stc Block Diagram

    BLK1 CPU1 (BIST’ed core) DBIST CNTRL STC REG STC_BYPASS / BLOCK ATE Interface DBIST CNTRL CPU2 (BIST’ed VBUSP core) Interface Test controller CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 345 After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken to idle mode by executing the CPU Idle Instruction asm(“ WFI”). SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 346: Application Self-Test Flow Chart

    Read the SelfTest and system status registers. SelfTest Done? Retrieve state of CPU and Registers CPU reset asserted and continue Application Software. CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 347 VCLK = 100 MHz VCLK = 80 MHz STCCLK = 90 MHz STCCLK = 50MHz STCCLK = 80 MHz 364 µs 655.20 µs 409.50 µs SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 348 Section 8.4.9 CPU2_CURMISR1 CPU2 Current MISR Register Section 8.4.9 CPU2_CURMISR0 CPU2 Current MISR Register Section 8.4.9 STCSCSCR Signature Compare Self-Check Register Section 8.4.10 CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 349: Stc Global Control Register 0 (Stcgcr0) [Offset = 00]

    NOTE: On a power-on reset or system reset, this register resets to its default values. Also, this register automatically resets to its default values at the completion of a self-test run. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 350: Self-Test Run Timeout Counter Preload Register (Stctpr) [Offset = 08H]

    NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a power-on reset or system reset, this register resets to all zeroes. CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 351: Stc Current Interval Count Register (Stccicr) [Offset = 10H]

    NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 or on a power-on reset, the current interval counter resets to the default value. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 352: Self-Test Global Status Register (Stcgstat) [Offset = 14H]

    Additionally when the STC_ENA key is written from a disabled state to enabled state, the two status flags get cleared to their default values. This register gets reset to its default value with power-on reset assertion. CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 353: Self-Test Fail Status Register (Stcfstat) [Offset = 18H]

    This register gets reset to its default value with power-on reset assertion. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 354: Cpu1 Current Misr Register (Cpu1_Curmisr3) [Offset = 1Ch]

    GOLDEN MISR value copied from ROM. NOTE: This register gets reset to its default value with power-on or system reset assertion. CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 355: Cpu2 Current Misr Register (Cpu2_Curmisr3) [Offset = 2Ch]

    GOLDEN MISR value copied from ROM. NOTE: This register gets reset to its default value with power-on or system reset assertion. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 356: Signature Compare Self-Check Register (Stcscscr) [Offset = 3Ch]

    Signature compare logic self-check is enabled. This allows a fault to be inserted using the FAULT_INS field. Any other Signature compare logic self-check is disabled The FAULT_INS field has no effect in this value case. CPU Self-Test Controller (STC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 357 In case there is no failure (TEST_DONE = 1 and TEST_FAIL = 0), the CPU self-test is completed successfully. • Recover the CPU status, configuration registers and continue the application software. SPNU503C – March 2018 CPU Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 358 ........................... Topic Page ....................Main Features ....................Block Diagram ..................... Module Operation ................CCM-R4F Control Registers CPU Compare Module for Cortex-R4F (CCM-R4F) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 359: Block Diagram

    2 cycles delay compare CCM-R4F error CPU1CLK (Error compare Signaling Module) CPU 1 CPU 2 Checker CPU Master CPU 2 cycles delay CPU2CLK SPNU503C – March 2018 CPU Compare Module for Cortex-R4F (CCM-R4F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 360 CPU signals. Also during self-test, only the compare unit logic is tested and not the memory mapped register controls for the CCM-R4F. The self-test is not interruptible. CPU Compare Module for Cortex-R4F (CCM-R4F) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 361 Compare Mismatch Test. There is no error signal is sent to ESM if the expected errors are seen with each pattern. SPNU503C – March 2018 CPU Compare Module for Cortex-R4F (CCM-R4F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 362 “CCM-R4F - self-test” is expected after the self-test error forcing mode completes. Once the expected errors are seen, the application can clean the error through ESM module. CPU Compare Module for Cortex-R4F (CCM-R4F) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 363 Table 9-3. CCM-R4F Control Registers Offset Acronym Register Description Section CCMSR CCM-R4F Status Register Section 9.4.1 CCMKEYR CCM-R4F Key Register Section 9.4.2 SPNU503C – March 2018 CPU Compare Module for Cortex-R4F (CCM-R4F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 364: Ccm-R4F Status Register (Ccmsr) (Address = Ffff F600H)

    The contents of this register should be interpreted in context of what test was selected. That is what mode is CCM operating in. CPU Compare Module for Cortex-R4F (CCM-R4F) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 365: Ccm-R4F Key Register (Ccmkeyr) (Address = Ffff F604H)

    Note: It is recommended to not write any other key combinations. Invalid keys will result in values switching operation to lockstep mode. SPNU503C – March 2018 CPU Compare Module for Cortex-R4F (CCM-R4F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 366 Low-Power Oscillator and Clock Detect (LPOCLKDET) ......................... 10.5 ..................10.6 PLL Control Registers ............10.7 Phase-Locked Loop Theory of Operation ..................10.8 Programming Example Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 367 – Configurable modulation depth (NV) • The slip control circuitry provides flexible response to a PLL failure (slip) including reset or automatic switch over to oscillator. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 368: Clock Path From Oscillator Through Pll To Device

    PLL as clock source for GCLK and HCLK is the memory wrapper to insure that access times are maintained correctly. Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 369: Clock Generation Path

    The crystal is a very tight bandpass filter while a resonator is a somewhat wider bandpass. The load circuitry pulls the center frequency of the bandpass. Texas Instruments strongly encourages each customer to submit samples of the device to the resonator/crystal vendor for validation. The vendor is equipped to determine what load capacitances will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.

  • Page 370: Oscillator Implementation

    The oscillator disable signal places the oscillator into a low-power state, disconnects the feedback (bias) resistor between OSCIN and OSCOUT, and OSCIN is grounded. Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 371 • GCM clock source 0 (replacing the oscillator) • GCM clock source 1 (replacing the PLL) • GCM clock source 5 as HF LPO SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 372 If the HF LPO is valid and the oscillator is not valid, the clock detect circuitry will become active (overriding the oscillator invalid signal) after 16K LF LPO cycles (about 200ms). Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 373 Once the HF LPO is determined to be in-range with the initial HFTRIM setting from the OTP, the crystal oscillator may be used as a reference against which the HF LPO and LF LPO may be further adjusted. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 374: Operation Of The Fm-Pll Module

    ÷1 - ÷8 ÷1 - ÷32 ÷1 - ÷64 ÷NF ÷1 - ÷256 CLKIN ---------------- - x NF x -------- - --- - PLLCLK Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 375 PLL clock frequency (and hence also the VCLK frequency). As such, this frequency change could violate the requirements for an asynchronous clock domain. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 376 A M O U N T S P R R AT E (11) NOTE: Modulation should be enabled after Lock Enable modulation after the lock is completed. Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 377 CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register (CSVSTAT) of the System and Peripheral Control Registers. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 378 Typically, any change to the REFCLKDIV field or large changes to the PLLMUL field in the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires a complete disable-and-relock strategy. Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 379 = 6 × T Enable OSCIN Disable clocks after lock = 150 × T Enable OSCIN Change ODPLL = 3 × T ODPLL OSCIN SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 380: Pll Slip Detection And Reset/Bypass Block Diagram

    PLL Bypass CLK Clock Control Module PLL CLK Input from FMzPLL Oscillator Bypass on Slip BPOS Slip Detector To Device Reset BPOS Reset on Slip Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 381 After this step, the valid flag is unlocked and cleared if it was previously set. 4. Re-enable PLL2 with CSDISCLR. 5. Switch the clock domains back to PLL2. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 382 SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT. 5. Compute the modulation depth as: æ ´ ´ ö CAPTURE COUNT ç ç ÷ ÷ Depth è ø CLKOUT COUNT (12) Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 383 Any PLL error can be handled by the CPU. PLL2 is programmed through PLLCTL3. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 384 Table 10-5. LPOCLKDET Module Registers Offset Acronym Register Description Section FFFF FF88h LPOMONCTL LPO/Clock Monitor Control Register Section 2.5.1.30 FFFF FF8Ch CLKTEST Clock Test Register Section 2.5.1.31 Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 385: Ssw Pll Bist Control Register 1 (Sswpll1) [Offset = Ff24H]

    If EXT_COUNTER_EN = 0, COUNTER_EN = 1 indicates that the counters are still active. If EXT_COUNTER_EN = 1, COUNTER_EN = 1 enables the counters. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 386: Ssw Pll Bist Control Register 2 (Sswpll2) [Offset = Ff28H]

    0-FFFF FFFFh Capture count. This register returns the value of the capture count. When EXT_COUNTER_EN = 0, this counter increments within a fixed modulation window. When EXT_COUNTER_EN = 1, this counter increments based upon the oscillator. Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 387: Ssw Pll Bist Control Register 3 (Sswpll3) [Offset = Ff2Ch]

    Field Value Description 31-0 SSW_CAPTURE_COUNT 0-FFFF FFFFh Value of CLKout count register. This counter increments based upon the PLL output (prior to the R-divider). SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 388: Basic Pll Circuit

    Figure 10-10. PFD Timing Input reference Feedback divider output Leading phase Lagging phase Down Interpulse slope caused by filter time constant and leakage VCO control voltage Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 389: Pll Modulation Block Diagram

    Figure 10-11. PLL Modulation Block Diagram post-ODCLK Output CLK INTCLK PLL CLK CLKIN ÷ ÷ ÷ ÷ Feedback ÷ Divider SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 390: Frequency Vs. Time

    Choose NR = 5, NS = 20 and set NF = 90 or choose NR = 4, NS = 25 and set NF = 72. CLKIN CLKIN (17) Oscillator and PLL SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 391 The Output CLK is centered in the range from 150MHz to 550MHz at 360MHz. NF = 90 falls within the multiplier range from 1 to 256. OD is selected so that post-ODCLK meets the device specification. SPNU503C – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 392 Topic Page ..................... 11.1 Introduction ..................... 11.2 Module Operation ..........11.3 Clock Source Selection for Counter0 and Counter1 ..................11.4 DCC Control Registers Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 393: Dcc Operation

    Error (to ESM) Compare and Control Logic Done (to VIM) Preload Count 1 Reload Reload Single Sequence Clock 1 Mode Down Counter 1 SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 394 • The module is reset or restarted by the application, OR • Counter0, Valid 0 and Counter1 all reach 0 without any error Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 395: Counter Relationship

    Figure 11-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting Error Count0 Clock0 Valid0 Count1 Clock1 time reload Counter1 does not reach 0 before VALID0 reaches 0 SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 396: Clock1 Faster Than Clock0 - Results In An Error And Stops Counting

    1 time reload An error signal is generated since Count1 does not reach 0 in the Valid0 window. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 397: Clock0 Not Present - Results In An Error And Stops Counting

    ESM whenever this DCC error is indicated. Refer the device datasheet to identify the ESM group and channel where the DCC error is connected. SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 398 The selection of the clock sources for counter0 and coutner1 is done by a combination of the KEY, CNT0 CLKSRC, and CNT1 CLKSRC control fields of the CNT0CLKSRC and CNT1CLKSRC registers. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 399 DCC Counter1 Value Register Section 11.4.9 DCCCNT1CLKSRC DCC Counter1 Clock Source Selection Register Section 11.4.10 DCCCNT0CLKSRC DCC Counter0 Clock Source Selection Register Section 11.4.11 SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 400: Dcc Global Control Register (Dccgctrl) [Offset = 00]

    Write: Load counters with their seed values and begin counting. It is recommended to write Ah to enable counters to protect against single-bit errors. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 401: Dcc Revision Id Register (Dccrev) [Offset = 4H]

    NOTE: Seed for Counter0 must be non-zero The DCC must only be enabled after programming a non-zero value in the COUNT0 SEED register. SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 402: Dcc Valid0 Seed Register (Dccvalid0Seed) [Offset = Ch]

    NOTE: Seed for Counter0 must be non-zero The DCC must only be enabled after programming a non-zero value in the COUNT1 SEED register. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 403: Dcc Status Register (Dccstat) [Offset = 14H]

    Read: DCC error has not occurred. Write: Writing 0 has no effect. Read: An error has occurred. Write: Writing 1 in privileged mode clears the ERR flag. SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 404: Dcc Counter0 Value Register (Dcccnt0) [Offset = 18H]

    NOTE: Reads may not return exact current value of counter Reading the counter0 value while counting is enabled may not return the exact value of the counter0. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 405: Dcc Valid0 Value Register (Dccvalid0) [Offset = 1Ch]

    NOTE: Reads may not return exact current value of counter Reading the counter1 value while counting is enabled may not return the exact value of the counter1. SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 406: Dcc Counter1 Clock Source Selection Register (Dcccnt1Clksrc) [Offset = 24H]

    Writes in privileged mode select the clock source for counter1. Refer to the device datasheet for available clock source options and the KEY required to enable these options for counter1. Dual-Clock Comparator (DCC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 407: Dcc Counter0 Clock Source Selection Register (Dcccnt0Clksrc) [Offset = 28H]

    Reads in any operating mode return the current value of CLKSRC. Writes in privileged mode select the clock source for counter0. Refer to the device datasheet for available clock source options for counter0. SPNU503C – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 408 ........................... Topic Page ......................12.1 Overview .................... 12.2 Module Operation ............12.3 Recommended Programming Procedure .................... 12.4 Control Registers Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 409: Block Diagram

    Interrupt Handling Interrupt error_group1 Interrupt Enable High-Priority High-Priority Interrupt Priority Interrupt Handling Interrupt error_group2 ERROR Pin Enable Device Output ERROR Error Signal error_group3 Handling SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 410: Interrupt Response Handling

    ERROR Pin Enable Controlled by: ESMIEPSR1, Low-Time ESMIEPCR1 Counter Preload ESMIEPSR4, Error Signal (LTCP ESMIEPCR4 Control error_group2 Low-Time Device Counter Output ERROR (LTC) error_group3 ESMEPSR Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 411 ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1, ESMSR4, and the shadow register ESMSSR2. Reading ESMIOFFLR will also not clear the ESMSR1 and ESMSR4. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 412: Error Pin Timing - Example 1

    In this case, the ERROR pin is set to high immediately after ERROR pin ERROR_low reset request is received. Figure 12-6. ERROR Pin Timing - Example 3 failure ERROR pin reset request ERROR ERROR_low Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 413: Error Pin Timing - Example 4

    To avoid this scenario, the application must write 5h followed by 0 to the ESM Error Key Register (ESMEKR). In this case, the ERROR pin will go high and then go low again to indicate the second failure. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 414: Error Pin Timing - Example 7

    Figure 12-9. ERROR Pin Timing - Example 7 failure Write “0101” to ESMEKR Write “1010” to ESMEKR Write “0” to ESMEKR ERROR ERROR_low Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 415: Esm Initialization

    ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served, the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared by RST. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 416 Interrupt Level Set Register 4 Section 12.4.21 FFFF F554h ESMILCR4 Interrupt Level Clear Register 4 Section 12.4.22 FFFF F558h ESMSR4 ESM Status Register 4 Section 12.4.23 Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 417: Esm Enable Error Pin Action/Response Register 1 (Esmeepapr1) [Address = Ffff F500H]

    Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 418: Esm Interrupt Enable Set Register 1 (Esmiesr1) [Address = Ffff F508H]

    Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register. Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 419: Esm Interrupt Level Set Register 1 (Esmilsr1) [Address = Ffff F510H]

    Read: Interrupt of channel x is mapped to high-level interrupt line. Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in the ESMILSR1 register. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 420: Esm Status Register 1 (Esmsr1) [Address = Ffff F518H]

    Note: In normal operation, the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2. Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 421: Esm Status Register 3 (Esmsr3) [Address = Ffff F520H]

    Note: This flag will be set to 1 after PORRST. The value will be unchanged after RST. The ERROR pin status remains unchanged after RST. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 422: Esm Interrupt Offset High Register (Esmioffhr) [Address = Ffff F528H]

    Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect. Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 423: Esm Interrupt Offset Low Register (Esmiofflr) [Address = Ffff F52Ch]

    Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high-level interrupt line only. User and privileged mode (write): Writes have no effect. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 424: Esm Low-Time Counter Register (Esmltcr) [Address = Ffff F530H]

    16-bit preload value for the ERROR pin low-time counter. Defines the minimum period for which the ERROR pin will be driven to 16384 VCLK cycles. Note: Only LTCP[15] and LTCP[14] are configurable (privileged mode write). Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 425: Esm Error Key Register (Esmekr) [Address = Ffff F538H]

    Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST). SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 426: Esm Influence Error Pin Set Register 4 (Esmiepsr4) [Address = Ffff F540H]

    Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register. Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 427: Esm Interrupt Enable Set Register 4 (Esmiesr4) [Address = Ffff F548H]

    Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 428: Esm Interrupt Level Set Register 4 (Esmilsr4) [Address = Ffff F550H]

    Read: Interrupt of channel x is mapped to high-level interrupt line. Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in the ESMILSR4 register. Error Signaling Module (ESM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 429: Esm Status Register 4 (Esmsr4) [Address = Ffff F558H]

    Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. SPNU503C – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 430 ........................... Topic Page ......................13.1 Overview ..................... 13.2 Module Operation ..................13.3 RTI Control Registers Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 431 Schnittstellen für die Elektronik im Kraftfahrzeug, or Open Systems and the Corresponding Interfaces for Automotive Electronics) as well as OSEK/time-compliant operating systems, but is not limited to it. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 432: Rti Block Diagram

    The counter values can be determined by reading the respective counter registers or by generating a hardware event which captures the counter value into the respective capture register. Both functions are described in the following sections. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 433: Counter Block Diagram

    To Compare Free Running Counter RTICLK Up Counter Unit RTIFRC1 Up Counter Register RTIUC1 Capture Up Capture Free Running Counter Counter RTICAUC1 RTICAFRC1 SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 434 RTICLK if RTICPUCy ≠ (2 +1) x RTIUDCPy COMPx RTICLK if RTIUDCPy = 0, x (RTICPUCy + 1) x 2 (24) COMPx RTICLK Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 435: Compare Unit Block Diagram (Shows Only 1 Of 4 Blocks For Simplification)

    RTIUC0 happens, RTICPUC0 should be set to a value so the clock frequency RTIUC0 outputs is approximately the same as the NTUx frequency. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 436: Timebase Control

    NOTE: To ensure the NTUx signal is properly detected, the NTUx period must be at least twice as long as the RTICLK period. Figure 13-5. Clock Detection Scheme RTIUC0 RTICPUC0 RTITBLCOMP RTITBHCOMP Active Edge time Detection NTUx Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 437: Switch To Ntux

    NTU pulse. Setting TBEXT = 0 will also switch the clock source for RTIFRC0 to RTIUC0. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 438: Missing Ntux Signal Example

    KEY [1:0] 16 bit out to 2 DWD down counter RTICLK RTIDWDCNTR Suspend nTRST DWD preload DWD ctrl DWD hardwired RTIDWDPRLD RTIDWDCTRL code Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 439: Dwd Operation

    DWWD is configured to generate a non-maskable interrupt on a window violation, the watchdog counter continues to count down. The NMI handler needs to clear the watchdog violation status flag(s) and then SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 440: Digital Windowed Watchdog Timing Example

    Value left shifted 11bits DWD can NOT be served in this period time Reset/NMI Config Write enable set DWD access Preload Keys to DWD Window Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 441 NTU signal of the suspended communication controller. This will be signaled with an TBINT interrupt so that software can resynchronize after the device exits halting debug mode. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 442 RTI Compare 1 Clear Register Section 13.3.37 RTICOMP2CLR RTI Compare 2 Clear Register Section 13.3.38 RTICOMP3CLR RTI Compare 3 Clear Register Section 13.3.39 Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 443: Rti Global Control Register (Rtigctrl) [Offset = 00]

    COS setting in the RTI module and the halting debug mode behavior of the communications controller. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 444: Rti Timebase Control Register (Rtitbctrl) [Offset = 04H]

    When the timebase supervisor circuit detects a missing clock edge, then the TBEXT bit is reset. Only the software can select whether the external signal should be used. RTIUC0 clocks RTIFRC0. NTU clocks RTIFRC0. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 445: Rti Capture Control Register (Rticapctrl) [Offset = 08H]

    RTIUC0 and RTIFRC0. Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 0. Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 1. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 446: Rti Compare Control Register (Rticompctrl) [Offset = 0Ch]

    Compare select 0. This bit determines the counter with which the compare value held in compare register 0 (RTICOMP0) is compared. Value will be compared with RTIFRC0. Value will be compared with RTIFRC1. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 447: Rti Free Running Counter 0 Register (Rtifrc0) [Offset = 10H]

    Note: If the preset value is bigger than the compare value stored in register RTICPUC0, then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 448: Rti Compare Up Counter 0 Register (Rticpuc0) [Offset = 18H]

    0 (RTIFRC0) when an event occurs, controlled by the external capture control block. A read of this register returns the value of RTIFRC0 on a capture event. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 449: Rti Capture Up Counter 0 Register (Rticauc0) [Offset = 24H]

    A write to this register presets the counter. The counter increments then from this written value upwards. Note: If counters must be preset, they must be disabled in the RTIGCTRL register to ensure consistency between RTIUC1 and RTIFRC1. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 450: Rti Up Counter 1 Register (Rtiuc1) [Offset = 34H]

    Note: If the preset value is bigger than the compare value stored in register RTICPUC1, then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 451: Rti Compare Up Counter 1 Register (Rticpuc1) [Offset = 38H]

    If CPUC1 ≠ 0, then = RTICLK/(RTICPUC1+1) FRC1 A read of this register returns the current compare value. A write to this register updates the compare value. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 452: Rti Capture Free Running Counter 1 Register (Rticafrc1) [Offset = 40H]

    RTICAFRC1 register, even if another capture event happens in between the two reads. A read of this register returns the value of RTIUC1 on a capture event. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 453: Rti Compare 0 Register (Rticomp0) [Offset = 50H]

    A read of this register will return the value to be added to the RTICOMP0 register on the next compare match. A write to this register will provide a new update value. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 454: Rti Compare 1 Register (Rticomp1) [Offset = 58H]

    A read of this register will return the value to be added to the RTICOMP1 register on the next compare match. A write to this register will provide a new update value. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 455: Rti Compare 2 Register (Rticomp2) [Offset = 60H]

    A read of this register will return the value to be added to the RTICOMP2 register on the next compare match. A write to this register will provide a new update value. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 456: Rti Compare 3 Register (Rticomp3) [Offset = 68H]

    A read of this register will return the value to be added to the RTICOMP3 register on the next compare match. A write to this register will provide a new update value. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 457: Rti Timebase Low Compare Register (Rtitblcomp) [Offset = 70H]

    A write to this register has the following effects: If TBEXT = 0: The compare value is updated. If TBEXT = 1: The compare value is not changed. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 458: Rti Set Interrupt Control Register (Rtisetintena) [Offset = 80H]

    SETDMA1 Set compare DMA request 1. Read: DMA request is disabled. Write: DMA request is unchanged. Read or Write: DMA request is enabled. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 459 Read or Write: Interrupt is enabled. SETINT0 Set compare interrupt 0. Read: Interrupt is disabled. Write: Corresponding bit is unchanged. Read or Write: Interrupt is enabled. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 460: Rti Clear Interrupt Control Register (Rticlearintena) [Offset = 84H]

    Clear compare DMA request 2. Read: DMA request is disabled. Write: Corresponding bit is unchanged. Read: DMA request is enabled. Write: DMA request is disabled. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 461 Write: Interrupt is disabled. CLEARINT0 Clear compare interrupt 0. Read: Interrupt is disabled. Write: Corresponding bit is unchanged. Read: Interrupt is enabled. Write: Interrupt is disabled. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 462: Rti Interrupt Flag Register (Rtiintflag) [Offset = 88H]

    Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. Read: No interrupt is pending. Write: Bit is unchanged. Read: Interrupt is pending. Write: Bit is cleared to 0. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 463: Digital Watchdog Control Register (Rtidwdctrl) [Offset = 90H]

    DWD is enabled, it can only be disabled by system reset or power on reset. However should the RTICLK source be changed to a source that is unimplemented it will have the same effect as disabling the watchdog. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 464: Digital Watchdog Preload Register (Rtidwdprld) [Offset = 94H]

    The expiration time of the DWD Down Counter can be determined with following equation: texp = (DWDPRLD+1) x 2 / RTICLK1 where: DWDPRLD = 0...4095 Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 465: Watchdog Status Register (Rtiwdstatus) [Offset = 98H]

    Write: Bit is unchanged. Read: Reset or NMI was generated. Write: Bit is cleared to 0. Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 466: Rti Watchdog Key Register (Rtidwdkey) [Offset = 9Ch]

    Watchdog is reset. E51Ah WDKEY is enabled for reset or NMI by next A35Ch. 2345h System reset or NMI; incorrect value written to WDKEY. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 467: Rti Watchdog Down Counter Register (Rtidwdcntr) [Offset = A0H]

    WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 468: Digital Windowed Watchdog Window Size Control (Rtiwwdsizectrl) [Offset = A8H]

    WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 469: Rti Compare Interrupt Clear Enable Register (Rtiintclrenable) [Offset = Ach]

    Privileged Write: Auto-clear for compare 0 interrupt becomes disabled. All other values Read: Auto-clear for compare 0 interrupt is enabled. Privileged Write: Auto-clear for compare 0 interrupt becomes enabled. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 470: Rti Compare 0 Clear Register (Rticmp0Clr) [Offset = B0H]

    Reads return the current compare clear value. A privileged write to this register updates the compare clear value. Real-Time Interrupt (RTI) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 471 Reads return the current compare clear value. A privileged write to this register updates the compare clear value. SPNU503C – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 472 ........................... Topic Page ......................14.1 Overview .................... 14.2 Module Operation ......................14.3 Example ..................14.4 CRC Control Registers Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 473 Generate DMA request per channel to initiate CRC value transfer. • Data trace capability on Peripheral Bus Master, Flash and System RAM data buses. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 474 Time Logic Preload CRC Timeout Interrupt Register Counter CH2_INT CRC_INT CH3_INT CH4_INT 16 Bit 16 Bit Sector Sector Count Counter Preload Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 475 PSA Signature Register and compare the calculated signature to the pre-determined CRC signature value. In Full-CPU mode, neither interrupt nor DMA request is generated. All counters are also disabled. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 476 CPU itself can also perform data transfer by reading from the memory system and perform write operation to PSA Signature Register if CPU has enough throughput to handle data patterns transfer. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 477 The PSA Signature Register can be updated with new signature before the host CPU is able to retrieve it. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 478 CRC_SCOUNT_REGx of the respective channel. CRC_PCOUNT_REGx multiplies CRC_SCOUNT_REGx and multiplies transfer size of each data pattern should give the total block size in number of bytes. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 479 Sector 1 CRC value Sector 2 CRC value PSA Sig Reg CRC Value Reg DMA channel 15 Sector n CRC value SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 480 CRC failure, it is advisable to use the following equation during CRC and DMA setup: CRC Pattern Count × CRC Sector Count = DMA Element Count × DMA Frame Count Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 481 PSA Sector Signature Register. If the host CPU does not read the signature from PSA Sector Signature Register before it is updated again with a new signature value, then an overrun interrupt is generated. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 482 Note: No timeout interrupt is generated in this example since each block of data patterns are compressed in 3 ms and DMA does initiate a block transfer every 10 ms. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 483 DMA is set up in fixed priority scheme and DMA is serving other higher priority channels at the time before it can service the timer request. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 484 During data trace mode, all interrupts and DMA request logic are inactive. For non double word read on the data bus, all un-selected byte lanes are padded with zero during compression. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 485 • Different sizes of burst operation. • Aligned and unaligned accesses. • Abort is generated for any illegal address accesses. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 486 CPU. The entire operation will continue again when DMA responds to the DMA request from both the timer and CRC Controller. The CRC is performed totally without any CPU intervention. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 487 CPU. Responding to the DMA interrupt CPU can restart the CRC routine by generating a software DMA request onto channel 2 again. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 488 A memory area with 2Mbyte is to be checked with the help of the CPU. CRC verification is to be performed every 1K byte. In CPU mode, the CRC Value Register is not updated and contains indeterminate data. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 489 Channel 2 Raw Data Low Register Section 14.4.33 RAW_DATAREGH2 Channel 2 Raw Data High Register Section 14.4.34 140h CRC_BUS_SEL Data Bus Selection Register Section 14.4.35 SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 490 Power Down. When set, CRC module is put in power-down mode CRC is not in power-down mode. CRC is in power-down mode. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 491 Register without any compression. This mode can be used to plant seed value into the PSA register. AUTO mode Semi-CPU mode Full-CPU mode SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 492 CRC Fail Interrupt is disabled. CRC Fail Interrupt is enabled. Privileged mode (write): Has no effect. CRC Fail Interrupt is enabled. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 493 Compression Complete Interrupt is disabled. Compression Complete Interrupt is enabled. Privileged mode (write): Has no effect. Compression Complete Interrupt is enabled. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 494 CRC Fail Interrupt is disabled. CRC Fail Interrupt is enabled. Privileged mode (write): Has no effect. CRC Fail Interrupt is disabled. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 495 Compression Complete Interrupt is disabled. Compression Complete Interrupt is enabled. Privileged mode (write): Has no effect. Compression Complete Interrupt is disabled. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 496 User and Privileged mode (read): No CRC Fail Interrupt is active. CRC Fail Interrupt is active. Privileged mode (write): Has no effect. Bit is cleared. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 497 No Compression Complete Interrupt is active. Compression Complete Interrupt is active. Privileged mode (write): Has no effect. Bit is cleared. 14.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG) SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 498 Ch2 Compression Complete Bh-10h Reserved Ch1 Overrun Ch2 Overrun 13h-18h Reserved Ch1 Underrun Ch2 Underrun 1Bh-20h Reserved Ch1 Timeout Ch2 Timeout 23h-FFh Reserved Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 499 Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 500 In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 501 CRC for an entire block needs to complete before a timeout interrupt is generated. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 502 31-0 CRC1 Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 503 Field Descriptions Field Description 31-0 PSASECSIG1 Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 504 Channel 2 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 505 In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 506 CRC for an entire block needs to complete before a timeout interrupt is generated. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 507 31-0 CRC2 Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 508 Field Descriptions Field Description 31-0 PSASECSIG2 Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 509 Table 14-38. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions Field Description 31-0 RAW_DATA2 Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. SPNU503C – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 510 Enable/disables the tracing of instruction TCM Tracing of Flash data bus has been disabled. Tracing of Flash data bus has been enabled. Cyclic Redundancy Check (CRC) Controller Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 511 Interrupt Vector Table (VIM RAM) ..................15.5 VIM Wakeup Interrupt ..................15.6 Capture Event Sources ......................15.7 Examples ..................15.8 VIM Control Registers SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 512 - Interrupt Generation Table Index Index Vector Vector Configuration Register RegisterRegister Register Request Request t Vector (Direct CAPEVT[1:0] Wakeup_INT Hardware VBUSP Vector) VIC Port Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 513 A write of 1 to CPSR bit 7 disables the IRQ from CPU. However, a write of 1 to CPSR bit 6 leaves it unchanged. Example 15-2 also shows how to disable the IRQ through CPSR. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 514 15.8.9) in the VIM. This is not necessary if any of the three previous methods are used as the interrupt request bit in the VIM will be automatically cleared when the vector is read. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 515 PROGRAMMABLE INTERRUPT VECTOR TABLE FIQINDEX IRQINDEX Phantom Vector Channel 0 Vector Channel 1 Vector Channel 94 Vector TO CPU VIC Port Register Register IRQVECREG FIQVECREG SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 516 (REQENASET and REQENACLR). When channel 2 is enabled, the priority is: INT0 INT1 INT2 INT3 Disabling channel 2, the priority becomes: INT0 INT1 INT3 INT2 Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 517 Peripheral 94 CHAN94 Channel 94 Vector 0xFFF8217C NOTE: CHAN0 and CHAN1 are hard wired to INT_REQ0 and INT_REQ1, so they cannot be remapped. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 518 FIQ and IRQ classes) to the CPU. Within the FIQ and IRQ classes of interrupts, the lowest channel has the highest priority interrupt. The channel number is programmable through register CHANMAPx. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 519 NOTE: The interrupt vector table only has 96 entries, one phantom vector and 95 interrupt channels. Channel 95 does not have a dedicated vector and shall not be used. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 520 This initialization is only required when vectored interrupts are used, index interrupt management does not need the table to be initialized. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 521 Figure 15-8. Parity Bit Mapping 32-bit only accessible 0xFFF82000 Word 0 Word 1 Word 2 Word 3 0xFFF82400 Read 0 Read 0 Read 0 Read 0 SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 522 INT_REQ1 WAKEUP1 WAKEENA.1 Controlled by: WAKEENASET.1 WAKEENACLR.1 INT_REQ2 WAKE_INT WAKEUP2 WAKEENA.2 Controlled by: WAKEENASET.2 WAKEENACLR.2 INT_REQ95 WAKEUP95 WAKEENA.95 Controlled by: WAKEENASET.95 WAKEENACLR.95 Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 523 ; Mask 0-31 bits except bit 24 in Sys ; Ctrl Reg of CORTEX-R4 MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0 ; Enable bit 24 MOV PC, LR SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 524 ‘PC - 0x1B0’, which is ‘0x18 or 0x1C + 0x08 - 0x1B0 = 0xFFFFFE70 or 0xFFFFFE74’. These are the address of IRQVECREG and FIQVECREG, which store the pending ISR address. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 525 The difference is that the CPU will not read from the 0x18 location during IRQ interrupt, but will jump directly to the corresponding ISR routine. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 526 Section 15.8.14 FIQVECREG FIQ Interrupt Vector Register Section 15.8.15 CAPEVT Capture Event Register Section 15.8.16 80h-DCh CHANCTRL VIM Interrupt Control Register Section 15.8.17 Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 527 The VIM parity is enabled. Note: To avoid soft error to disable VIM parity checking, it is recommended to write Ah to enable parity checking. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 528 FBPARERR until the PARFLG register has been cleared. This register provides the address of the ISR that will restore the integrity of the Interrupt Vector Table. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 529 The VIM offset registers are read only. They are updated continuously by the VIM. When an interrupt is serviced, the offset vectors show the index for the next highest pending interrupt or 0x0 if no interrupt is pending. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 530 FIQ interrupt. In case there is no other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will read the phantom interrupt address. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 531 FIQ or IRQ. Bit FIRQPRx[95:2] corresponds to request channel[95:2]. Interrupt request is of IRQ type. Interrupt request is of FIQ type. Reserved Read only. Writes have no effect. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 532 Clears the interrupt pending status flag. This write-clear functionality is intended to allow clearing those interrupts which have been signaled to VIM before enabling the interrupt channel, if they are undesired. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 533 Write: A write of 0 has no effect. Read or Write: The interrupt request channel is enabled. Reserved Read only. Writes have no effect. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 534 Write: A write of 0 has no effect. Read: The interrupt request channel is enabled. Write: The interrupt request channel is disabled. Reserved Read only. Writes have no effect. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 535 Read: Interrupt request channel is disabled. Write: A write of 0 has no effect. Read or Write: The interrupt request channel is enabled. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 536 Write: A write of 0 has no effect. Read: The wake-up interrupt channel is enabled. Write: The wake-up interrupt channel is disabled. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 537 FIQ interrupt. In case there is no other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will read the phantom interrupt address. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 538 Capture event source 0 mapping control. These bits determine which interrupt request maps to the capture event source 0 of the RTI: Interrupt request 0. Interrupt request 1. Interrupt request 95. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 539 Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx is set with the interrupt request. Reserved Reads are indeterminate and writes have no effect. SPNU503C – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 540 Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx is set with the interrupt request. Vectored Interrupt Manager (VIM) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 541 This chapter describes the direct memory access (DMA) controller..........................Topic Page ......................16.1 Overview ..................... 16.2 Module Operation ............... 16.3 Control Registers and Control Packets SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 542 Peripheral bus. Figure 16-1. DMA Block Diagram Register Bank Peripheral Bus Local RAM (with parity) DMAREQ Port B Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 543 Frame 3 Frame 4 Element 1 Element 2 Element 3 Element 4 Element 5 Element 6 Element 7 Element 8 DMAREQ SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 544 This field stores the absolute 32-bit source address of the DMA transfer. 16.2.4.2 Initial Destination Address This field stores the absolute 32-bit destination address of the DMA transfer. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 545 Current Transfer Count Working CP1 Current Source Address Current Destination Address Current Transfer Count 0x8F0 Current Destination Address Working CPnn Current Source Address SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 546 The current destination address field contains the current working destination address during a DMA transaction. The current destination address is incremented during post-increment addressing mode or indexing mode. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 547 This example can be applied to either source or destination indexing and assumes the following setup. Element Size = 16 bit Element Count = 4 Frame Count = 4 SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 548 Control Packet 14 Control Packet 15 Triggered Channels The above figure illustrates that by default Lower the channel number, higher the Priority. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 549 Pending triggere d Start/S top se rving SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 550 (eg., SCITD register). User should configure DMA to avoid data unpacking if the Destination is configured as Constant Addressing Mode write to avoid data loss. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 551 Equation 26 is not a multiple of the write element size. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 552 NOTE: Since peripherals are slower, it is advised to use data packing feature with caution for reading data from peripherals. Improper use might delay servicing other pending DMA channels. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 553 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6] SPI1, SPI3, SPI5 receive in standard SPI mode SPI1, SPI3, SPI5 transmit in standard SPI mode SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 554 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / DMAREQ[31] MIBSPI5[0] SPI1, SPI3, SPI5 receive in standard SPI mode SPI1, SPI3, SPI5 transmit in standard SPI mode Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 555 Group B - Interrupts (FTC, LFS, HBC, and BTC) are not routed out. User software should configure only Group A interrupts. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 556 Frame Transfer Complete Ch0 FTC0AB FTCA Frame Transfer Complete Ch31 FTC31AB This figure is applicable for the HBC, LFS, and BTC interrupt. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 557 DMA performs minimal bus cycles on AHB bus. In addition, the bypass feature allows arbitration between channels that can be carried out at a source element granularity. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 558 In this example CH1 is Chained to CH0. When CH0 is triggered CH1 is captured as pending in the Channel Pending Register (Section 16.3.1.2) even when it is not triggered. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 559 For example, if region 0 and region 1 overlap, the access permissions defined for region 0 will take precedence since region 0 registers are before region 1. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 560 DMA Parity Error Address Register (Section 16.3.1.53). The address is frozen from being updated until it is read by the bus master. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 561 To allow for parity calculation during initialization, the parity functionality has to be enabled as discussed in Section 16.2.15. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 562 BER Interrupt Flag Register Section 16.3.1.35 14Ch FTCAOFFSET FTCA Interrupt Channel Offset Register Section 16.3.1.36 150h LFSAOFFSET LFSA Interrupt Channel Offset Register Section 16.3.1.37 Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 563 Current Source Address Register Section 16.3.2.7 804h CDADDR Current Destination Address Register Section 16.3.2.8 808h CTCOUNT Current Transfer Count Register Section 16.3.2.9 SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 564 Read and write: The DMA state machine and all control registers are in software reset. Control packets are not reset when DMA software reset is active. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 565 Note: The status of a channel currently in DMA's execution queue remains active even if emulation mode is entered or DMA is disabled via DMA_EN bit. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 566 Read: The corresponding channel is disabled for HW triggering. Write: No effect. Read: The corresponding channel is enabled for HW triggering. Write: The corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 567 Reading from SWCHENAS gives the status (enabled/disabled) of channels 0 through 15. The corresponding channel is not triggered by SW request. The corresponding channel is triggered by SW request. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 568 Read: The corresponding channel is assigned to the low-priority queue. Write: No effect. Read and write: The corresponding channel is assigned to high-priority queue. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 569 Read: The corresponding channel is disabled for interrupt. Write: No effect. Read and write: The corresponding channel is enabled for interrupt. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 570 Read: The corresponding channel is disabled for interrupt. Write: No effect. Read: The corresponding channel is enabled for interrupt. Write: The corresponding channel is disabled for interrupt. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 571 Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. DMA request line 0 triggers channel 3. DMA request line 31 triggers channel 3. 20h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 572 Channel 7 assignment. This bit field chooses the DMA request assignment for channel 7. DMA request line 0 triggers channel 7. DMA request line 31 triggers channel 7. 20h- Reserved Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 573 Channel 11 assignment. This bit field chooses the DMA request assignment for channel 11. DMA request line 0 triggers channel 11. DMA request line 31 triggers channel 11. 20h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 574 Channel 15 assignment. This bit field chooses the DMA request assignment for channel 15. DMA request line 0 triggers channel 15. DMA request line 31 triggers channel 15. 20h- Reserved Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 575 Reads return 0. Writes have no effect. CH7PA These bit fields determine to which port channel 7 is assigned. Port B Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 576 Reads return 0. Writes have no effect. CH15PA These bit fields determine to which port channel 15 is assigned. Port B Reserved Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 577 The LFS interrupt of the corresponding channel is routed to Group A. The LFS interrupt of the corresponding channel is routed to Group B. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 578 The BTC interrupt of the corresponding channel is routed to Group A. The BTC interrupt of the corresponding channel is routed to Group B. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 579 Read: The corresponding FTC interrupt of a channel is disabled. Write: No effect. Read: The corresponding FTC interrupt of a channel is enabled. Write: The corresponding FTC interrupt is disabled. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 580 Write: No effect. Read: The LFS interrupt of the corresponding channel is enabled. Write: The LFS interrupt of the corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 581 Write: No effect. Read: The HBC interrupt of the corresponding channel is enabled. Write: The HBC interrupt of the corresponding channel is disabled. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 582 Write: No effect. Read: The BTC interrupt of the corresponding channel is enabled. Write: The BTC interrupt of the corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 583 Read: An FTC interrupt of the corresponding channel is not pending. Write: No effect. Read: An FTC interrupt of the corresponding channel is pending. Write: The flag is cleared. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 584 Read: An HBC interrupt of the corresponding channel is not pending. Write: No effect. Read: An HBC interrupt of the corresponding channel is pending. Write: The flag is cleared. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 585 Imprecise Error and DMA Write Imprecise Error asserted to the ESM module directly, which are detected at the device level. See the ESM error mapping for the DMA Read/Write Imprecise Error. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 586 Table 16-45. LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions Field Value Description 31-8 Reserved Reads return 0. Writes have no effect. These bits should always be programmed as 0. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 587 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 15 is causing the pending interrupt Group A. 11h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 588 Table 16-47. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions Field Value Description 31-8 Reserved Reads return 0. Writes have no effect. These bits should always be programmed as 0. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 589 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 15 is causing the pending interrupt Group A. 11h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 590 Table 16-49. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions Field Value Description 31-8 Reserved Reads return 0. Writes have no effect. These bits should always be programmed as 0. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 591 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 15 is causing the pending interrupt Group B. 11h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 592 Table 16-51. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions Field Value Description 31-8 Reserved Reads return 0. Writes have no effect. These bits should always be programmed as 0. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 593 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 15 is causing the pending interrupt Group B. 11h- Reserved SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 594 The fixed priority scheme is used. The rotation priority scheme is used. 15-0 Reserved Reads return 0. Writes have no effect. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 595 Note: This bit should be cleared to 0 during normal operation. RAM Test Control is disabled. RAM Test Control is enabled. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 596 Note: This bit is reset when Test reset (nTRST) is low. Debug is disabled. The watch point checking logics is enabled. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 597 Allows the corresponding bit in the WPR register to be used for address matching for a watch point. Masks the corresponding bit in the WPR register and is disregarded in the comparison. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 598 Port B Active Channel Destination Address. This register contains the current destination address of the active channel as broadcasted in Section 16.3.1.3 for Port B. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 599 Port B active channel element count. These bits contain the current element count value of the active channel as broadcasted in Section 16.3.1.3 for Port B. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 600 Note: It is recommended to write Ah to enable parity check, to guard against soft error from flipping PARITY_ENA to a disable state. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 601 SUSPEND is high, this address is frozen even when read. Note: The error address register will not be reset by PORRST nor by any other reset source. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 602 Region 2 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 603 Region 0 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 604 Region 0 fault. This bit determines whether an access permission violation was detected in this region. Read: No fault was detected. Write: No effect. Read: A fault was detected. Write: The bit was cleared. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 605 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 606 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 607 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 608 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 609 Table 16-73. Initial Destination Address Register (IDADDR) Field Descriptions Field Value Description 31-0 IDADDR 0-FFFF FFFFh Initial destination address. These bits give the absolute 32-bit destination address (physical). SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 610 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 611 Post-increment Reserved Indexed ADDMW Addressing mode write. Constant Post-increment Reserved Indexed Auto-initiation mode. Auto-initiation mode is disabled. Auto-initiation mode is enabled. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 612 Source address frame index. These bits define the offset to be added to the source address after element count reached 1. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 613 Current destination address. These bits contain the current working absolute 32-bit destination address (physical). These bits are only updated after a channel is arbitrated out of the priority queue. SPNU503C – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 614 Current element transfer count. These bits return the current remaining element counts. CTCOUNT register is only updated after a channel is arbitrated out of the priority queue. Direct Memory Access Controller (DMA) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 615 This chapter describes the external memory Interface (EMIF)..........................Topic Page ..................... 17.1 Introduction ................. 17.2 EMIF Module Architecture ....................17.3 EMIF Registers ..................17.4 Example Configuration SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 616 Note that the EMIF module does not support Mobile SDRAM devices. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 617 SDRAM EMIF_nRAS interface EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EDMA Asynchronous EMIF_nOE interface EMIF_nWAIT Master Peripherals EMIF_nWE EMIF_BA[1:0] Shared SDRAM EMIF_nDQM[1:0] and asynchronous interface EMIF_DATA[15:0] EMIF_ADDR[21:0] SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 618 When interfacing to an asynchronous device, these pins are connected to byte enables. See Section 17.2.6 for details. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 619 Several EMIF signals are multiplexed with other functions on this microcontroller. Please refer to the I/O Multiplexing Module chapter of the technical reference manual for more information on how to enable the output of these EMIF signals. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 620 EMIF_nCS[0] EMIF_nRAS EMIF_nCAS EMIF_nWE EMIF_BA[1:0] EMIF_A[12:11] EMIF_A[10] EMIF_A[9:0] Bank/X ACTV Bank READ Bank Column Column Bank Column Column Mode Mode Mode REFR SLFR External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 621 2M x 16 EMIF_nCS[0] x 4 bank EMIF_nCAS nCAS EMIF_nRAS nRAS EMIF_nWE EMIF_CLK EMIF_CKE EMIF_BA[1:0] BA[1:0] EMIF_A[11:0] A[11:0] EMIF_nDQM[0] LDQM EMIF_nDQM[1] UDQM EMIF_D[15:0] DQ[15:0] SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 622 SDRAM A[11:0] EMIF EMIF_A[11:0] 128M bits ×16 SDRAM A[11:0] EMIF EMIF_A[11:0] 256M bits SDRAM A[12:0] EMIF EMIF_A[12:0] 512M bits SDRAM A[12:0] EMIF EMIF_A[12:0] External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 623 • RR = f / (Required SDRAM Refresh Rate) EMIF_CLK More information about the operation of the SDRAM refresh controller can be found in Section 17.2.5.6. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 624 6. Finally, the EMIF performs a refresh cycle, which consists of the following steps: a. Issuing a PRE command with EMIF_A[10] held high if any banks are open b. Issuing an REF command External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 625 200 μs (sometimes 100 μs). For example, an EMIF_CLK frequency of 100 MHz would require setting RR to 2501 (9C5h) or higher to meet a 200 μs constraint. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 626 Multiple auto-refresh cycles are performed at the completion of the current access until the Refresh Release urgency level is reached. At that point, the EMIF can begin servicing any new read or write requests. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 627 EMIF_CLK. If the frequency of EMIF_CLK changes while the SDRAM is not in Self-Refresh Mode, Procedure B in Section 17.2.5.5 should be followed to reinitialize the device. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 628 If the PD bit is cleared while in the power-down state, the EMIF will come out of the power-down state. The EMIF: • Drives EMIF_CKE high. • Enters its idle state. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 629 NOP commands between various commands during an access. Refer to the register description of SDTIMR in Section 17.3.6 for more details on the various timing parameters. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 630 NOP commands during various cycles of an access. Refer to the register description of SDTIMR in Section 17.3.6 for more details on the various timing parameters. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 631 Row Address EMIF_BA[1:0] Column Address EMIF_nDQM[0] NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit SDRAM memories. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 632 EMIF's external pins used in interfacing with an asynchronous device. In EMIF_nCS[n], n = 2, 3, or 4. Figure 17-7. EMIF Asynchronous Interface EMIF EMIF_nCS[n] EMIF_nWE EMIF_nOE EMIF_WAIT EMIF_D[x:0] EMIF_nDQM[x:0] EMIF_A[x:0] EMIF_BA[1:0] External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 633 EMIF_BA[1] A[0] b) EMIF to 16-bit memory interface Figure 17-9. Common Asynchronous Interface EMIF 16−bit asynchronous device EMIF_nCS[n] EMIF_nWE EMIF_nDQM[1:0] BE[1:0] EMIF_D[15:0] DQ[15:0] SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 634 SDRAM accesses. Refer to the datasheet of the external asynchronous device to determine the appropriate setting for this field. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 635 (INTMSKSET). AT_MASK_CLR Asynchronous Timeout Mask Clear. Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout occurs. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 636 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 637 Figure 17-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enable EMIF_A/EMIF_BA Address EMIF_D Data EMIF_nOE EMIF_nWE SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 638 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 639 Figure 17-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enable EMIF_A/EMIF_BA Address Address EMIF_D Data EMIF_nOE EMIF_nWE SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 640 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 641 Figure 17-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enables EMIF_A/EMIF_BA Address Data EMIF_D EMIF_nOE EMIF_nWE SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 642 If this is the case, the EMIF instead enters directly into the turn-around period for the pending read or write operation. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 643 R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize the EMIF_nWAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in CEnCFG. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 644 For information about the self-refresh state, see Section 17.2.5.7. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 645 Table 17-23 contains a brief summary of the interrupt status and control bit fields. See Section 17.3 for complete details on the register fields. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 646 For details on EMIF signal multiplexing, see the I/O Multiplexing Module chapter of the technical reference manual. 17.2.12 Memory Map For information describing the device memory-map, see your device-specific datasheet. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 647 See Section 17.2.5.7 for details on the operation of the EMIF when in the self-refresh state. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 648 If EMIF is used to interface to an external SDRAM, it is recommended to burst as much as possible to normal memory to improve the interface bandwidth. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 649 EMIF in power down mode. 17.2.16 Emulation Considerations EMIF memory controller remains fully functional during emulation halts in order to allow emulation access to external memory. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 650 LEGEND: R = Read only; -n = value after reset Table 17-25. Module ID Register (MIDR) Field Descriptions Field Value Description 31-0 Module ID of EMIF. See the device-specific data manual. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 651 Maximum extended wait cycles. The EMIF will wait for a maximum of (MAX_EXT_WAIT + 1) × 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 652 Reserved Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 653 Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the SDRAM timing register (SDTIMR). SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 654 Asynchronous Data Bus Width. This field defines the width of the asynchronous device data bus. 8-bit data bus 16-bit data bus 2h-3h Reserved External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 655 Reserved Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 656 This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, minus 1. T_XS = Txsr / t EMIF_CLK External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 657 Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the AT_MASKED bit in the EMIF interrupt masked register (INTMSK). SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 658 Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit as well as the AT bit in the EMIF interrupt raw register (INTRAW). External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 659 Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the AT_MASK_CLR bit in the EMIF interrupt mask clear register (INTMSKCLR). SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 660 Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the AT_MASK_SET bit in the EMIF interrupt mask set register (INTMSKSET). External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 661 Page Mode enable for NOR Flash connected on CS2. Page mode is disabled for this chip select. Page mode is enabled for this chip select. SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 662 Table 17-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface Field Value Purpose 1 then 0 To place the EMIF into the self refresh state External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 663 A[12:1] DQ[15:0] EMIF_ADDR [18:13] nRESET Reset nRESET A[18:13] RY/BY nBYTE0 nBYTE1 FLASH A[0] 512k x 16 A[12:1] DQ[15:0] nRESET A[18:13] RY/BY nBYTE0 nBYTE1 SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 664 Figure 17-28. SDRAM Timing Register (SDTIMR) 0 0110 T_RFC T_RP Rsvd T_RCD Rsvd T_WR 0100 0110 0000 T_RAS T_RC Rsvd T_RRD Reserved External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 665 Figure 17-29. SDRAM Self Refresh Exit Timing Register (SDSRETR) 0000 0000 0000 0000 Reserved 000 0000 0000 0 0110 Reserved T_XS SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 666 = 100 MHz EMIF_CLK Figure 17-30. SDRAM Refresh Control Register (SDRCR) 0 0000 0000 0000 Reserved Reserved 0 0110 0001 1010 (61Ah) Reserved External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 667 Figure 17-31. SDRAM Configuration Register (SDCR) 0 0000 Reserved Reserved Reserved 00 0000 Reserved Reserved Reserved Reserved Reserved Reserved BIT11_9LOCK Reserved IBANK Reserved PAGESIZE SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 668 EHEL Figure 17-33) Figure 17-32. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms Setup Hold Strobe EMIF_CLK EMIF_nCS[n] EMIF_A/ EMIF_BA EHQZ ELQV Data EMIF_D EMIF_nOE External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 669 For Writes, the W_STROBE field should be set to satisfy the Flash's nCE Pulse Width constraint, t ELEH W_STROBE >= t × f ELEH EMIF_CLK W_STROBE >= 50 ns × 100 MHz - 1 W_STROBE >= 4 SPNU503C – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 670 Figure 17-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3)) 0010 W_SETUP W_STROBE 0110 W_STROBE W_HOLD R_SETUP 001011 R_SETUP R_STROBE R_HOLD ASIZE External Memory Interface (EMIF) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 671 This chapter describes the parameter overlay module (POM)..........................Topic Page ..................... 18.1 Introduction ..................... 18.2 Module Operation ..................18.3 POM Control Registers SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 672 TO flag, so that any further aborts are not misinterpreted as having been caused due to a timeout from the POM. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 673 POM by any other bus master would result in a deadlock situation (system hang). Other bus masters need to access the target internal or external memory directly. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 674 This flag must be cleared so that any further aborts are not misinterpreted as having been caused by timeout on a POM access. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 675 POM Component ID 1 Register Section 18.3.25 FF8h POMCOMPONENTID2 POM Component ID 2 Register Section 18.3.26 FFCh POMCOMPONENTID3 POM Component ID 3 Register Section 18.3.27 SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 676 POM is held in reset. NOTE: The key should be written to 5h, to avoid single bit flips inadvertently turning on the module. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 677 Do not modify this bit. Leave it in its reset state. Modifying the bit while the POM module is switched on can result in unexpected behavior. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 678 POM module is enabled (ON/OFF = Ah). Read: No timeout occurred. Write: No effect. Read: Timeout occurred. Write: Bit is cleared. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 679 NOTE: If the region start address is programmed to a non-region size boundary, the region will begin at the next lower region size boundary. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 680 LEGEND: R = Read only; -n = value after reset Table 18-9. POM Integration Control Register (POMITCTRL) Field Descriptions Field Value Description 31-0 Reserved Reads return 0, writes have no effect. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 681 The module is claimed. Read: This claim tag bit is not implemented. Write: No effect. Read: This claim tag is implemented. Write: Set claim tag. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 682 Write: No effect. Write: Clear claim tag. CLR0 The module is claimed. Read: Current claim tag value. Write: No effect. Write: Clear claim tag. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 683 LEGEND: R = Read only; -n = value after reset Table 18-14. POM Authentication Status Register (POMAUTHSTATUS) Field Descriptions Field Value Description 31-0 Reserved Reads return 0, writes have no effect. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 684 Table 18-16. POM Device Type Register (POMDEVTYPE) Field Descriptions Field Value Description 31-8 Reserved Reads return 0, writes have no effect. Sub Type Other Major Type Debug Control Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 685 LEGEND: R = Read only; -n = value after reset Table 18-18. POM Peripheral ID 5 Register (POMPERIPHERALID5) Field Descriptions Field Value Description 31-0 Reserved Reads return 0, writes have no effect. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 686 LEGEND: R = Read only; -n = value after reset Table 18-20. POM Peripheral ID 7 Register (POMPERIPHERALID7) Field Descriptions Field Value Description 31-0 Reserved Reads return 0, writes have no effect. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 687 Reads return 0, writes have no effect. JEP106 Identity Part of TI JEDEC number. Code Part Number Reads 0, since POMREV defines the module. SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 688 LEGEND: R = Read only; -n = value after reset Table 18-24. POM Peripheral ID 3 Register (POMPERIPHERALID3) Field Descriptions Field Value Description 31-0 Reserved Reads return 0, writes have no effect. Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 689 Table 18-26. POM Component ID 1 Register (POMCOMPONENTID1) Field Descriptions Field Value Description 31-8 Reserved Reads return 0, writes have no effect. Component Class CoreSight Component Preamble Preamble SPNU503C – March 2018 Parameter Overlay Module (POM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 690 Table 18-28. POM Component ID 3 Register (POMCOMPONENTID3) Field Descriptions Field Value Description 31-8 Reserved Reads return 0, writes have no effect. Preamble Preamble Parameter Overlay Module (POM) SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 691 ADC Special Modes ..............19.9 ADC Results’ RAM Special Features ............ 19.10 ADEVT Pin General Purpose I/O Functionality ..................19.11 ADC Control Registers SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 692 Figure 19-1. Channel Assignments of Two ADC Cores AD1IN[7:0] ADC1 AD1EVT 12 Bit AD1IN[23:8] CCAD SSAD Interface REFHI REFLO ADC2 12 Bit AD2EVT Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 693 Conversion Result ADIN0 Sequencer and ADC Results’ Memory Interface ADC Results’ Controller Memory VBUS Interface for Access to ADC Registers VBUSP SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 694 – - AD (27) REFHI REFLO 4096 x(InputVoltage - AD REFLO DigitalResult -------------------------------------------------------------------------------------- - 0.5 – - AD (28) REFHI REFLO Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 695 Configure the mode of conversion: single conversion sequence or continuous conversions • Configure the input channel sampling time • Configure the interrupt and/or DMA request generation conditions SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 696 Group2 will be automatically be configured to be in a single conversion sequence mode. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 697 ADBNDEND contains a 3-bit field called BNDEND that configures the total memory available. The ADC module can support up to 1024 buffers. The device supports a maximum of 64 buffers for both the ADC modules. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 698 ADEVBUFFER Reserved EV_DR Reserved G1_CHID 0xB0 to 0xCF EMPTY ADG1BUFFER Reserved G1_DR Reserved G2_CHID 0xD0 to 0xEF EMPTY ADG2BUFFER Reserved G2_DR Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 699 Conversion word 0 0xFF3E0004 0xFF3A0004 Conversion word 1 0xFF3E0008 0xFF3A0008 Conversion word 2 0xFF3E01F8 0xFF3A01F8 Conversion word 62 0xFF3E00FC 0xFF3A00FC Conversion word 63 SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 700 7, and so on. So the application can selectively read the conversion results for only one channel if so desired. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 701 7. Read the conversion results by reading from the Group1 FIFO access location (ADG1BUFFER) or by reading directly from the Group1 results’ memory. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 702 STOP EMPTY Reserved 0x074 ADG2SR Reserved MEM_ BUSY STOP EMPTY The following sections describe each of these group configuration options separately. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 703 Group2 is automatically reset to single-conversion mode, and the G2_MODE bit in the ADG2MODECR register is cleared to reflect the single-conversion mode of Group2. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 704 FIFO. This does not clear the contents of the results FIFO; only the ADC module is allowed to overwrite the FIFO’s contents with new conversion results starting from the first location. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 705 Therefore, the CHID bit for a group can be changed dynamically without affecting that group’s ongoing conversions. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 706 CPU or the DMA. Alternatively, the application program can set the group’s OVR_RAM_IGN bit and allow the ADC module to overwrite the group’s results’ memory contents with new conversion results. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 707 The group’s BLOCKS field is essentially the same as the group’s THRESHOLD field in the group’s interrupt control register described in Section 19.5.2. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 708 However, a read from the magnitude threshold interrupt offset register in emulation mode does not affect the interrupt flag register or the interrupt offset register. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 709 The BRIDGE_EN and HILO bits (ADCALCR.9:8) control the voltage to the calibration reference device shown in Figure 19-13. The positions of the switches in calibration mode are listed in Table 19-1. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 710 7. Compute the error correction value using calibration data saved in memory. 8. Load the ADCALR register with the 2s complement of the computed error correction value. 9. Disable calibration mode. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 711 3. The actual value of the real middle point is obtained by computing the average of these two results. [D(cal1)+D(cal2)] /2; Figure 19-12 summarizes the mid-point calibration flow. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 712 V(cal2) = [VREFLO*R1+VREFHI*R2] / (R1 + R2) D(cal2) [V(cal1) + V(cal2)] / 2 = (VrefHi-VrefLo) / 2 [D(cal1) + D(cal2)] / 2 = D(cal) Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 713 R1 || R2 connected to V REFLO via R1 || R2 connected to V REFHI Switches refer to Figure 19-13. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 714 AD Shorted to AD REFHI REFHI REFHI REFHI approx. AD Shorted to AD REFLO REFLO REFLO REFLO Unknown Open REFHI REFLO Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 715 If a conversion is ongoing when this bit is set, the ADC module will wait until the current conversion completes before allowing the ADC module clock to be stopped. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 716 Figure 19-15. Timing for Sample Capacitor Discharge Mode Sample cap discharge time Sampling time Tdischarge T samp Conversion of last value sampled ADINx Vreflo Start Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 717 RAM. See Figure 19-16. The CPU can now manually insert parity errors. Note that the ADC RAM only supports 32-bit accesses. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 718 Figure 19-17. GPIO Functionality of ADxEVT Output enable ADxEVT Data out Data in Pull control disable Pull control logic Pull select Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 719 PULDIS = 0 for enabling pull control, 1 for disabling pull control PULSEL = 0 for pull-down functionality, 1 for pull-up functionality SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 720 Section 19.11.39 ADEVEMUBUFFER ADC Event Group Results Emulation FIFO Register Section 19.11.40 ADG1EMUBUFFER ADC Group1 Results Emulation FIFO Register Section 19.11.41 Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 721 ADC Parity Control Register Section 19.11.66 184h ADPARADDR ADC Parity Error Address Register Section 19.11.67 188h ADPWRUPDLYCTRL ADC Power-Up Delay Control Register Section 19.11.68 SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 722 The ADC core and digital logic are configured to be in 12-bit resolution. 30-25 Reserved Read returns 0. Writes have no effect. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 723 No ADC conversions can occur. The input channel select registers: ADEVSEL, ADG1SEL, and ADG2SEL are held at their reset values. ADC conversions can now proceed as configured. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 724 For more details on the ADC Self Test Mode, please refer to Section 19.8.2. Any operation mode read/write: ADC Self Test mode is disabled. ADC Self Test mode is enabled. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 725 Section 19.8.1 for more details on the ADC calibration mode. Any operation mode read/write: Calibration mode is disabled. Calibration mode is enabled. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 726 EV_MODE FRZ_EV RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 727 The Event Group conversion result is read out as an 8-bit value in the “read from Event Group FIFO” mode. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 728 Group are converted before the ADC can switch over to servicing any other conversion group. Event Group conversions are frozen whenever there is a request for conversion from Group1 or Group2. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 729 FRZ_G1 RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 730 The Group1 conversion result is read out as a 10-bit value in the “read from Group1 FIFO” mode. The Group1 conversion result is read out as an 8-bit value in the “read from Group1 FIFO” mode. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 731 ADC can switch over to servicing any other conversion group. Group1 conversions are frozen whenever there is a request for conversion from Event Group or Group2. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 732 FRZ_G2 RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 733 The Group2 conversion result is read out as a 10-bit value in the “read from Group2 FIFO” mode. The Group2 conversion result is read out as an 8-bit value in the “read from Group2 FIFO” mode. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 734 ADC can switch over to servicing any other conversion group. Group2 conversions are frozen whenever there is a request for conversion from Event Group or Group1. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 735 The ADC module allows a trigger source to be selected for the Event Group from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 736 The ADC module allows a trigger source to be selected for the Group1 from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 737 The ADC module allows a trigger source to be selected for the Group2 from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 738 No interrupt is generated if the Event Group threshold counter reaches zero. An Event Group threshold interrupt is generated if the Event Group threshold counter reaches zero. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 739 No interrupt is generated if the Group1 threshold counter reaches zero. A Group1 threshold interrupt is generated if the Group1 threshold counter reaches zero. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 740 No interrupt is generated if the Group2 threshold counter reaches zero. A Group2 threshold interrupt is generated if the Group2 threshold counter reaches zero. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 741 Event Group interrupt threshold register. This bit can be cleared by writing a 1 ; writing a 0 has no effect. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 742 Group1 interrupt threshold register. This bit can be cleared by writing a 1 ; writing a 0 has no effect. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 743 Group2 interrupt threshold register. This bit can be cleared by writing a 1 ; writing a 0 has no effect. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 744 Group1 threshold counter is not decremented. Please refer to Section 19.5.2 for more details on the threshold interrupts. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 745 Group2 threshold counter is not decremented. Please refer to Section 19.5.2 for more details on the threshold interrupts. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 746 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return zeros, writes have no effect. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 747 ADC module generates a DMA transfer when the ADC has written to the Event Group memory. The EV_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 748 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return zeros, writes have no effect. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 749 ADC module generates a DMA transfer when the ADC has written to the Group1 memory. The G1_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 750 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return zeros, writes have no effect. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 751 ADC module generates a DMA transfer when the ADC has written to the Group2 memory. The G2_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 752 A total of 2 × (BNDB - BNDA) buffers are available in the ADC results memory for storing Group1 conversion results. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 753 64 buffers each for ADC1 as well as ADC2. 4h-7h Reserved. These combinations must not be used. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 754 G1_ACQ value properly considering the frequency of the ADCLK signal. Please refer to the device datasheet to determine the minimum sampling time for this device. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 755 G2_ACQ value properly considering the frequency of the ADCLK signal. Please refer to the device datasheet to determine the minimum sampling time for this device. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 756 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 757 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 758 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 759 The channels marked by the bit positions that are set to ‘1’ will be converted in ascending order when the Event Group is triggered. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 760 The channels marked by the bit positions that are set to ‘1’ will be converted in ascending order when the Group1 is triggered. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 761 The channels marked by the bit positions that are set to ‘1’ will be converted in ascending order when the Group2 is triggered. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 762 ADC State Machine Current State. These bits reflect the current state of the state machine and are reserved for use by TI for debug purposes. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 763 A level higher than or equal to the midpoint reference voltage was measured at the last conversion for this channel. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 764 This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event Group results’ memory with just one instruction. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 765 ARM LDMIA instruction to read out up to 8 conversion results from the Group1 results’ memory with just one instruction. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 766 ARM LDMIA instruction to read out up to 8 conversion results from the Group2 results’ memory with just one instruction. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 767 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 768 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 769 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 770 Any operating mode read/write: ADEVT is an input pin; the output buffer is disabled. ADEVT is an output pin; the output buffer is enabled. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 771 ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. Any operating mode read: Logic LOW present on the ADEVT pin. Logic HIGH present on the ADEVT pin. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 772 Output value on the ADEVT pin is unchanged. Output logic LOW on the ADEVT pin, if the pin is configured to be an output pin. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 773 Any operating mode read/write: Pull on ADEVT pin is enabled. Pull on ADEVT pin is disabled. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 774 After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Event Group settings. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 775 After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Group1 settings. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 776 After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Group2 settings. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 777 COMP_CHIDx R/W-0 Reserved CHN_THR_ CMP_GE_LTx COMPx R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 778 The ADC module will check if the conversion result is greater than or equal to the reference value (fixed threshold or COMP_CHIDx conversion result). Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 779 The ADC module will not mask the corresponding bit for the comparison. The ADC module will mask the corresponding bit for the comparison. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 780 Any operation mode read/write for each bit: The enable status of the corresponding magnitude compare interrupt is left unchanged. The corresponding magnitude compare interrupt is disabled. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 781 Magnitude compare interrupt # 2 is pending. Magnitude compare interrupt # 3 is pending. 4h-Fh Reserved. These combinations do not occur. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 782 If the application needs the Group1 memory to always be overwritten with the latest available conversion results, then the OVR_G1_RAM_IGN bit in the Group1 operating mode control register (ADG1MODECR) needs to be set to 1. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 783 Event Group conversion result will be stored. This is specified in terms of the buffer number. The application can read this register to determine the number of valid Event Group conversion results available until that time. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 784 Group2 conversion result will be stored. This is specified in terms of the buffer number. The application can read this register to determine the number of valid Group2 conversion results available until that time. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 785 System module. Any operation mode read, privileged mode write: Parity check is disabled. Any other Parity check is enabled. SPNU503C – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 786 This register defines the number of VCLK cycles that the ADC state machine has to wait after releasing the ADC core from power down before starting a new conversion. Please refer to Section 19.8.3 for more details. Analog To Digital Converter (ADC) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 787 Overview ................20.2 N2HET Functional Description ....................20.3 Angle Functions ................... 20.4 N2HET Control Registers ....................20.5 HWAG Registers ....................20.6 Instruction Set SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 788 Overview www.ti.com 20.1 Overview The N2HET is a fifth-generation Texas Instruments (TI) advanced intelligent timer module. It provides an enhanced feature set compared to previous generations. This timer module provides sophisticated timing functions for real-time applications such as engine management or motor control. The high resolution hardware channels allow greater accuracy for widely used timing functions such as period and pulse measurements, output compare, and PWMs.
  • Page 789 HETFLG. 31:0 32 ALU Priority 2 HETOFF2.7:0 HETPRY.31:0 Rotate/ Shift by N HETDIN.31:0 HET[31:0] CONTROL HETDSET.31:0 HETDOUT.31:0 HETDIR.31:0 HETDCLR.31:0 HR clock HR block SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 790 MOV32 instruction is actually executed which occurs after the ECMP instruction matches its current compare value. This is the same behavior as one would expect from a double buffered hardware compare register. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 791 There is a new instruction WCAPE, which is a combination of a time stamp and an edge counter • New Open Drain, Pull Disable, and Pull Select registers SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 792 HR captures and compares are possible (up to N2HET clock accuracy) on the HR I/O pins. For more information about the HR I/O structure, see Section 20.2.5. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 793 HETOFF1.7:0 HETFLG. 31:0 Priority 2 T o VIM 32 Bit ALU HETOFF2.7:0 HETPRY.31:0 Rotate/ Shift By N Specialized timer micromachine To I/O Control SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 794 However other actions of the instruction including register and RAM updates will still be performed. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 795 MOV64 instruction in each low resolution loop, is required to control this particular program flow. NOTE: HR instructions must be placed in the main (full resolution) loop to ensure proper operation. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 796 The current N2HET instruction address can be inspected by reading the HETADDR register; this should be pointing to the instruction that caused the breakpoint. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 797 Table 20-1. N2HET RAM Base Addresses N2HET1 Base Address N2HET2 Base Address Memory 0xFF46_0000 0xFF44_0000 N2HET Instruction RAM (Program/Control/Data) 0xFF46_2000 0xFF44_2000 N2HET Parity RAM SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 798 NOTE: The external host interface supports any access size for reads, but only 32-bit writes to the N2HET RAM are supported. Reserved addresses should not be accessed, the result of doing so is indeterminate. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 799 Table 20-3. Pin Safe State Upon Parity Error Detection Safe State HETDIR HETPDR HETPSL Drive Low Drive High High Impedance SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 800 N2HET program must fit into one loop resolution clock period (LRP).A 3-bit prescaler dividing the HR clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution prescale factor code (HETPFR). See Table 20-5. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 801 LRPFC - Loop Resolution HRPFC - High Resolution HETPFR[10:8] Prescale Factor lr HETPFR[5:0] Prescale Factor hr 000000 000001 000010 000011 111101 111110 /128 111111 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 802 0 to 31 1/16 1/32 1/64 0 to 63 1/16 1/32 1/64 1/128 0 to 127 X = Non-relevant bit (treated as '0') High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 803 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 804 Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR) for writing, depending on the type of action to perform. The N2HET pins used as general-purpose inputs are sampled on each VCLK2 period. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 805 1, hr_data = 0x0 } ; 25 bit compare value is 1 and the 7-bit HR compare value is 0 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 806: Loop Resolution Instruction Execution Example

    HR mode (bit cleared to 0), but the other instructions can be used in standard resolution mode (bit set to 1). High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 807: Hr I/O Architecture

    HR prescale driver HR control logic Resolution clock Structure HR flags One Per HR up/down counter (7 bits) HR compare data HR register SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 808: Example Of Hr Structure Sharing For N2Het Pins 0/1

    The HET[1] HR structure is also connected to the HET[0] pin. The L00_PCNT data field is able to capture a high pulse and the L01_PCNT captures a low pulse on the same pin (N2HET [0] pin). High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 809: Xor-Shared Hr I/O

    LH = (2291 - 653) · HRP = 1638 HRP • Duty cycle = DC = LH / PWM_period = 1638 HRP / (2944·HRP) = 55.6 % SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 810: Symmetrical Pwm With Xor-Sharing Output

    Figure 20-15. AND-shared HR I/O HETAND0 N2HET HR 0 HET[0] HET[1] N2HET HR 1 HETAND0 High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 811: Hr0 To Hr1 Digital Loopback Logic: Lbtype[0] = 0

    Output is output Buffer LBSEL[0] value determines whether or not loopback is enabled for these two blocks HR 1 Output Buffer Pin 1 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 812: Hr0 To Hr1 Analog Loop Back Logic: Lbtype[0] = 1

    The loop back direction can be selected independent of the HETDIR register setting. • The pin that is not driven by the N2HET output pin actions can still be used as normal GIO pin. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 813: N2Het Input Edge Detection

    CNT and one ECMP instruction as shown below. The data field of the ECMP instruction is the 32-bit compare value, whereby the lower 7 bits represent the high resolution compare field. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 814: Ecmp Execution Timings

    MOV32. On execution of the MOV32, it moves its data field into the data field of the ECMP. The update of the duty cycle has to be made to the MOV32 data field instead of the ECMP data field. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 815: High/Low Resolution Modes For Ecmp And Pwcnt

    NOTE: The HR capture value written into RAM is shifted appropriately depending on the loop resolution prescale divide rate (lr). (See also Section 20.2.3.2). SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 816: Pcnt Instruction Timing (With Capture Edge After Hr Counter Overflow)

    Figure 20-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) HR clock Loop res clock PCNT CF HR counter HR capt. PCNT DF Input pin Input pin sync’d High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 817: Wcap Instruction Timing

    (2) is transferred to the valid bits (according the lr prescaler) of WCAP_DF[6:0]. Therefore, in the example 0x0240 is captured in WCAP_DF[31:0]. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 818: I/O Block Diagram Including Pull Control Logic

    The behavior of the input buffer, output buffer, and the pull control is summarized in Table 20-9. When an input buffer is disabled, it appears as a logic low to on-chip logic. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 819: N2Het Pin Disable Feature Diagram

    HETDOUT N2HET pin HETDIN to other N2HET pin structures nDIS pin* N2HET pin enable *nDIS pin realized by GIOA[5] (N2HET1) and GIOB[2] (N2HET2) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 820 • The accuracy of the output signal is +/- the counter clock frequency. Table 20-11 gives examples for a 100 MHz VCLK2 frequency. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 821: Suppression Filter Counter Operation

    Source No. Offset Value no interrupt Instruction 0, 32, 64... Instruction 1, 33, 65... Instruction 31, 63, 95... Program Overflow APCNT underflow: APCNT overflow SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 822: Interrupt Functionality On Instruction Level

    The interrupt with the highest priority is the one with the lower offset value. This scheme is hard-wired in the offset encoder. See Figure 20-28. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 823: Interrupt Flag/Priority Level Architecture

    34 Exc Int En 2 Exc Int flag 2 Offset index encoder HET interrupt priority 2 for level 2 offset vector priority SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 824: Request Line Assignment Example

    ACNT accumulates the fractions generated by SCNT. Figure 20-30 illustrates the basic operation of APCNT, SCNT, and ACNT. A N2HET timer program can only have one angle generator. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 825: Operation Of N2Het Count Instructions

    Figure 20-31. SCNT Count Operation Final Count = N0+nK Final Count = N1+mK Target=P(n-1) SCNT step counter N0+3K N1+2K N0+2K N1+K N0+K N2=N1+mK-P(n-1) N1=N0+nK-P(n-1) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 826: Acnt Period Variation Compensations

    Figure 20-32. ACNT Period Variation Compensations Deceleration Acceleration HET[2] ext. ref. signal P(n) APCNT P(n+1) period counter SCNT step counter ACNT angle generator Deceleration flag Acceleration flag High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 827: N2Het Timings Associated With The Gap Flag (Acnt Deceleration)

    Figure 20-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) Singularity HET[2] ext. ref. signal APCNT period counter Decel flag ACNT angle generator Gap flag Gap End Gap Start SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 828: N2Het Timings Associated With The Gap Flag (Acnt Acceleration)

    APCNT overflow interrupt flag located in the exceptions interrupt control register. In this situation, SCNT and ACNT continue to be executed using the maximum APCNT period count. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 829: Angle Generator Principle

    Programmable toothed-wheel input filter • Programmable active edge on toothed-wheel • Start bit synchronized to the tooth edge • Pin selection capability for toothed-wheel input SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 830: Hardware Angle Generator Block Diagram

    Figure 20-36. Hardware Angle Generator Block Diagram HWAG To CPU ICLK Gap Verification Toothed Wheel Angle Tick Generation Peripheral HWAG core HET Interface Angle increment HET Resolution To HET High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 831: Angle Tick Generation Principle

    Figure 20-37. Angle Tick Generation Principle Toothed wheel Angle Tick K Ticks P(n-1) P(n-1) P(n) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 832: New Angle Tick Generation Architecture

    When encountering an earlier active edge, the ACNT accumulates the fractions (angle ticks) generated by the SCNT and the remainder of the TCKC. For an example of angle generation using the time-based algorithm, see Figure 20-39. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 833: Angle Generation Using Time Based Algorithm

    Final Count = N1+mK P(n-1) SCNT N1 +4K N0 +4K N1 +3K N0 +3K N1 +2K N0 +2K N1 +K N0 +K N1=N0+nK-P(n-1) N2=N1+mK-P(n-1) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 834: Acnt During Acceleration And Deceleration

    When the ACNT contains a value equals to K times the teeth register, the PCNT, the TCNT and the ACNT are reset to begin a new revolution. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 835: Singularity Check, Acnt Reset And Timing Associated

    The tick counter is not reloaded because the Criteria flag is raised The Gap flag and tooth active edge reset, followed by ACNT SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 836: Example Of Hwag Start Sequence

    Figure 20-43. Example of HWAG Start Sequence TCNT Toothed wheel Start bit ACNT 2 x Step Width counter Angle Tick Synchronization time RUN time High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 837: Code

    NOTE: When stopping the HWAG, stop the angle increment delivered to the NHET and set it to zero. Reload the NHET counter with the same value of the angle counter (± corrections), if restarting the HWAG. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 838: Gap Verification Criteria For A 60-2 Toothed Wheel

    HWAG previous tooth period value register (HWAPCNT1). High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 839: Using The Arst Bit In A Toothed Wheel Without Singularity

    Figure 20-46. Figure 20-46. Using the ARST Bit in a Toothed Wheel Without Singularity Toothed wheel Gap flag ARST Tick counter ACNT SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 840: Windowing Filter For Toothed Wheel Input On Falling Active Edge

    512 × (1 – 0.75) = 128 When the tick counter reaches the filter register value, the toothed wheel input is unblocked. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 841: Filtering During Singularity Tooth

    4 = PCNT(n) > 2 × PCNT (n-1) during normal tooth • 5 = Bad active edge tooth • 6 = Gap flag • 7 = Angle increment overflow SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 842: Hwag Interrupt Block Diagram

    Sign. Not Found Priority Tooth Interrupt ACNT OVRF Criteria Found Bad active edge tooth Gap flag Angle Inc. OVRF OFFSET A OFFSET B High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 843 During debug mode, interrupts can occur and will wait until the CPU enters run mode again. If interrupts occur, they could affect synchronization with the toothed wheel SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 844: Hardware Angle Generator/High End Timer Interface

    NHET resolution clock. For an example of the angle count within the HWAG, see Figure 20- Figure 20-51. Angle Count Within the HWAG at Resolution Clock Angle count res. Angle increment High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 845: Angle Count Within The Nhet With Increments

    When the HET counter passes from 9 to 13, the equality compare can not match the compare value 10. Consequently, the angle position is missed! SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 846: Example Of Acmp Compare Within The Nhet

    Performing the following equations at the same time implements this compare: CMP > NHET angle counter – Angle increment CMP ≤ NHET angle counter High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 847: Nhet Interface Block Diagram

    11-bit counter of the NHET interface. This can happen if the number of angle ticks always exceeds 15 during one resolution. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 848 The maximum number of teeth is 256. This limits the number of increments per revolution to 512 steps × 256 teeth = 131 072 angle increments. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 849 Example: For a 60-2 at 10000 RPM, the tooth period is 100 µs and the step width is 512: 15 100 MaxHET resolution 2.93 s SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 850 1. Stop the HWAG 2. Reset ACNT 3. Reset tooth counter 4. Reset interrupt 5. Set start bit. The HWAG will restart on the tooth zero. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 851 HETLBPSEL Loop Back Pair Select Register Section 20.4.31 HETLBPDIR Loop Back Pair Direction Register Section 20.4.32 HETPINDIS NHET Pin Disable Register Section 20.4.33 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 852: Global Configuration Register (Hetgcr) [Offset = 00H]

    Timer RAM can be freely accessed during suspend. When set to 1, the suspend is ignored and the N2HET continues operating. N2HET stops when in suspend mode. N2HET ignores suspend mode and continues operation. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 853 N2HETs configuration, the slave N2HETs are waiting for the loop clock to come from the master before starting execution. Then, the timer address points automatically address 00h (corresponding to program start). SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 854: Prescale Factor Register (Hetpfr)

    (lr). /128 Reserved Reads return 0. Writes have no effect. HRPFC High-Resolution Pre-scale Factor Code. HRPFC determines the high-resolution prescale divide rate (hr). High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 855: N2Het Current Address (Hetaddr)

    Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation mode the corresponding flag is not cleared. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 856 Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation mode, the corresponding flag is not cleared. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 857 Read: Interrupt is disabled. Write: Writes have no effect. Read: Interrupt is enabled. Write: Interrupt is disabled. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 858 APCNT Underflow Exception Interrupt Priority Exception priority level 2. Exception priority level 1. PRGM_OVRFL_PRY ProgramOverflow Exception Interrupt Priority Exception priority level 2. Exception priority level 1. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 859 Read: Exception has not occurred since the flag was cleared. Write: No effect. Read: Exception has occurred since the flag was cleared Write: Clears the bit. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 860 Read: No N2HET instruction with an interrupt has been reached since the flag was cleared. Write: No effect. Read: A N2HET instruction with an interrupt has been reached since the flag was cleared. Write: Clears the bit. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 861 HR Output of HET[n+1] and HET[n] are not AND shared. HR Output of HET[n+1] and HET[n] are AND shared onto pin HET[n]. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 862 HR Input of HET[n+1] and HET[n] are not shared. HR Input of HET[n+1] and HET[n] are shared; both measure pin HET[n]. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 863 HR Output of HET[n+1] and HET[n] are not XOR shared. HR Output of HET[n+1] and HET[n] are XOR shared onto pin HET[n]. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 864 Read: Returns the information that request line n is enabled. Write: Writing a 1 to bit n disables the N2HET request line n. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 865 NOTE: Please refer to the device data sheet how each of the 8 N2HET request lines are connected to these modules. See also Section 20.2.9. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 866 Pin HET[n] is an output. NOTE: Table 20-9 shows how the register bits of DIR, PULDIS and PULSEL are affecting the N2HET pins. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 867 Pin HET[n] is at logic high (1) if the HETPDR[n] bit = 0 or the output is in high-impedance state if the HETPDR[n] bit = 1. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 868 HETDOUT unchanged. Reads from this address return the value of the HETDOUT register. Write: HETDOUT[n] is unchanged. Write: HETDOUT[n] is cleared. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 869 NOTE: See device data sheet for which pins provide programmable pullups/pulldowns. Table 20-9 shows how the register bits of HETDIR, HETPULDIS, and HETPSL are affecting the N2HET pins. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 870 If the HETPSL register specifies 1 for the pin, it will switch to high level. This behavior is independent of the value, which register HETPULDIS specifies for the corresponding pin. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 871 Write: Enable checking. NOTE: It is recommended to write Ah to enable error detection, to guard against soft errors flipping PARITY_ENA to a disable state. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 872 Reads return 0. Writes have no effect. NOTE: The Parity Error Address Register will not be reset, neither by PORRST nor by any other reset source. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 873 Table 20-45. Known State on Parity Error HETDIR[n] HETPDR[n] HETPSL[n] Known State on Parity Error High Impedance Drive Logic 0 Drive Logic 1 High Impedance SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 874 HETSFENA. The input noise suppression filter for pin HET[n] is disabled. The input noise suppression filter for pin HET[n] is enabled. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 875 LBPDIR n+1/n and type is selected by LBPTYPE n+1/n. The pin which is not driven by the N2HET pin actions can still be used as normal GIO pin. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 876 The HR structures on pins HET[n+1] and HET[n] connected with HET[n] as output and HET[n+1] as input. NOTE: The loop back direction can be selected independent on the HETDIR register setting. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 877 Logic high: Output buffer of the pin is enabled if pin nDIS = 1, HET_PIN_ENA = 1, and HETDIR = 1; or disabled if nDIS = 0, HETDIR = 0, or HET_PIN_ENA = 0. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 878 HWAG Current Teeth Number Register Section 20.5.17 HWAFIL HWAG Filter Register Section 20.5.18 HWAFIL2 HWAG Filter Register 2 Section 20.5.19 HWAANGI HWAG Angle Increment Register Section 20.5.20 High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 879 Read: Pin HET[2] is selected Write: Selects pin HET[2]. Default after reset for backwards compatibility Read: Pin HET[31] selected Write: Selects pin HET[31]. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 880 HWAG Module Power Down. This bit is implemented for legacy purposes, but has no functionality, however the HWAG module power down is controlled by the NHET power down. The HWAG cannot be powered down separately. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 881 (if set). The HWAG starts at the next active edge from the toothed wheel, once set. If the start bit is cleared to 0, the HWAG is stopped immediately. Do not start counting. Start counting. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 882 Singularity not found Tooth interrupt ACNT overflow PCNT(n) > 2 x PCNT (n-1) during normal tooth Bad active edge tooth Gap flag Angle increment overflow High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 883 Disable interrupt. See Table 20-57. Read: Corresponding interrupt is not enabled. Write: No effect. Read: Corresponding interrupt is enabled. Write: Disable corresponding interrupt. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 884 Reads return 0. Writes have no effect. CLRINTLVL[n] Clear Interrupt Level. See Table 20-57. Read: Low-priority interrupt. Write: No effect. Read: High-priority interrupt. Write: Set interrupt priority to low. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 885 HWAOFF registers will not clear a HWAFLG bit that is not enabled. See Table 20-57. Read: No interrupt is pending. Write: No effect. Read: Interrupt is pending. Write: Clear the corresponding interrupt flag. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 886 Singularity not found Tooth interrupt ACNT overflow PCNT(n) > 2 × PCNT (n-1) during normal tooth Bad active edge tooth Gap flag Angle increment overflow High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 887 Singularity not found Tooth interrupt ACNT overflow PCNT(n) > 2 × PCNT (n-1) during normal tooth Bad active edge tooth Gap flag Angle increment overflow SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 888 ACNT 0-FF FFFFh Angle Value. Provides the current angle value from the toothed wheel. This is equal to step width × teeth value. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 889 This period would not be accurate due to the fact that the PCNT counter is running at VCLK2 and that the peripheral bus is running at VCLK. Then, the value will have changed when used. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 890 65536, ..., 8, 4). The step count is decoded from the three LSBs using the following encoding: 4 ticks per period 8 ticks per period 16 ticks per period 65536 ticks per period 131072 ticks per period High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 891 Table 20-69. HWAG Current Teeth Number Register (HWATHVL) Field Descriptions Field Value Description 31-8 Reserved Reads return 0. Writes have no effect. THVL 0-FFh Teeth Value. Provides the current teeth number. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 892: Hwag Filter Register 2 (Hwafil2) Field Descriptions

    It allows the tooth signal to be taken into account by the HWAG. This function works only if the mode filtering is set. The value is calculated as shown in Section 20.3.2.2.5.1. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 893: Hwag Angle Increment Register (Hwaangi) Field Descriptions

    Angle Increment Value. Provides the current angle increment value. The value is incremented by the tick counter and is decremented by the NHET resolution clock. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 894: Instruction Summary

    If the high-resolution prescale value is set to /1, then this is also the same as the number of HR clock cycles. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 895: Flags Generated By Instruction

    Non Interrupt Capable Instructions ACMP ACNT ADCNST APCNT ADM32 DADM32 ECMP MOV32 ECNT MOV64 MCMP PCNT RADM64 PWCNT RCNT SCMP SHFT SCNT WCAP WCAPE SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 896 Pin Select: Selects the pin on which the action occurs. Enter the pin number. Default: pin 0 Location: Control field [12:8] except PCNT High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 897 Set low on match + reset to high on Z=1 (opposite action) Pulse High Set high on match + reset to low on Z=1 (opposite action) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 898 Default: ECMP Location: Control Field [6:5] Action C[6] C[5] Order ECMP SCMP MCMP1 REG_GE_DATA MCMP2 DATA_GE_REG High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 899 Register select Int. action Figure 20-111. ACMP Data Field (D31:D0) Data Reserved Cycles Register modified Selected register (A, B, R, S, or T) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 900 Angle inc. = NAF_global or hardware angle generator 11-bit input. The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 901 SWF0 and SWF1 (see information on SCNT). ACNT detects period variations of the external signal measured by APCNT and compensates related count errors. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 902 NAF = 1; If (Counter value != GapEnd) Register B = Data field register + 1; Data Field Register = Counter value + 1; High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 903 Jump to next program address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 904 A 25-bit value that is always added to the remote data field. Default: 0. hr_data Seven least significant bits of the data addition to the remote data field. Default: 0. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 905 Remote Data Field = Immediate Data Field + Remote Data Field; else Remote Data Field = Immediate Data Field + min. offset(bits C24:C0); Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 906 High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 907: Arithmetic / Bitwise Logic Sub-Opcodes

    C[7] = 1, C[2:1] = 00 S[24:0] = result [31:0] C[7] = 1, C[2:1] = 01 T[24:0] = result [31:0] C[7] = 0, C[2:1] = 10 SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 908: Shift Encoding

    ZERO, IMM, A, B, R, S, T, or ONES A,B,R,S,T, or NONE NONE == next[8:0] REM or REMP REMP REM or REMP == next[8:0] REMP == next[8:0] High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 909 001: // smode = Arithmetic Shift Right IR2[31 - scount : 0] = IR1[31:scount] if (scount>0) { IR2[31 : 31 - scount + 1] = IR1[31] SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 910 IN2 = IR2[31]; IZ2 = Set if IR2 == 0; IV2 = (IR2[31] XOR IR1[31]) OR IV1 case 110: // smode = Rotate Right High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 911 If (Init Flag == 1) ACF = 0; DCF = 1; GPF = 0; NAF = 0; else ACF, DCF, GPF, NAF remain unchanged; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 912 ON reinitializes the following system flags to these states: Acceleration flag (ACF) = 0 Deceleration flag (DCF) = 1 Gap flag (GPF) = 0 High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 913: Move Types For Adm32

    NAF = 0; else All flags remain unchanged; Jump to Next Program Address; Figure 20-126 Figure 20-127 illustrate the ADM32 operation for various cases. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 914 Register A, B, R, S, or T (dashed for R, S, T) Register A, B, R, S, or T (dashed for R, S, T) High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 915 T. When GPF = 0, the current period value is captured in the control field and in register T. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 916: Edge Select Encoding For Apcnt

    Rise2Rise Rising edge period Contains the 25-bit count value from the previous APCNT period. data 25-bit value serving as a counter. Default: 0. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 917 Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 918 Table 20-83 provides the branch condition encoding. event Specifies the event that triggers a jump to the indexed program address. Default: FALL High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 919: Branch Condition Encoding For Br

    Prv bit = Current Lx value of selected pin; (Always Executed) The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 920 (SWAG). When in angle count mode the angle increment value will be 0 or 1. It takes two cycles in this mode. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 921 0 and the Z system flag is set to 1. data Specifies the 25-bit integer value serving as a counter. Default: 0. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 922 Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 923 [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] remote={label | 9-bit unsigned integer} cntl_val={29-bit unsigned integer} data={25-bit unsigned integer} [hr_data= {7-bit unsigned integer}] SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 924: Dadm64 Control Field Description

    High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 925 Remote Data Field = Remote Data Field + Immediate Data Field; Register T = Immediate Data Field; Remote Control Field = Immediate Control Field; Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 926 The program flow can be modified when down counter value is zero by using the conditional address. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 927 Jump to conditional Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 928 Reserved En. pin Conditional address action Conditional address Pin select Action Register select Int. Figure 20-146. ECMP Data Field (D31:D0) Data HR Data High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 929 Specifies the value for the data field. This value is compared with the selected register. hr_data Specifies the HR delay. Default: 0. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 930 Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 931 NAF condition (NAF is defined in ACNT). This instruction can be used with all pins. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 932: Event Encoding Format For Ecnt

    Prv bit = Current Logic (Lx) value of selected pin; (Always executed) The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 933 Register select Int. Figure 20-152. MCMP Data Field (D31:D0) Data HR Data Cycles Register modified T (if save sub bit P[5] is set) SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 934: Magnitude Compare Order For Mcmp

    Specifies the value for the data field. This value is compared with the selected register. hr_data HR delay. The default value for an unspecified bit is 0. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 935 Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 936 C4:C3 = 01, where the remote data field is written with the immediate data field value. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 937: Move Type Encoding Selection

    Specifies a 25-bit integer value to be written to the remote data field or selected register. hr_data (Optional) HR delay. The default value for an unspecified bit is 0. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 938 Figure 20-159. MOV32 Move Operation for REMTOREG (Case 11) LSBs (HR data field) 25/32-bit move 32 bits Remote DF Register A, B, R, S, or T (dashed for R, S, T) High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 939 If (Init Flag == 1) ACF = 0; DCF = 1; GPF = 0; NAF = 0; else All flags remain unchanged; Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 940 [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] remote={label | 9-bit unsigned integer} cntl_val={29-bit unsigned integer} [data={25-bit unsigned integer] [hr_data= {7-bit unsigned integer} High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 941: Mov64 Control Field Descriptions

    Maintains the control field for the remote instruction. comp_mode Selects the comparison mode type to be used by the remote instruction. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 942: Comparison Type Encoding Format

    REG_GE_DATA MCMP2 DATA_GE_REG Execution Remote Data Field = Immediate Data Field; Remote Control Field = Immediate control Field; Jump to Next Program Address; High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 943 HR data field on the selected edge condition. If hr_lr is 0 (HIGH) then PCNT captures the HR delay. if hr_lr is 1 (LOW) then PCNT only captures at loop resolution. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 944: Counter Type Encoding Format

    2 edges. So first edge after turning on N2HET is used mainly for resetting the counter and start the period count. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 945 Jump to Next Program Address; The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 946 En. pin Conditional address action Conditional address Pin select Reserved Action Register select Int. Figure 20-169. PWCNT Data Field (D31:D0) Data HR Data High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 947 ON generates an interrupt when the data field value reaches 0. No interrupt is generated for OFF. Default: OFF. data 25-bit integer value serving as a counter. hr_data HR delay. Default: 0. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 948 Jump to Conditional Address The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 949 [brk={OFF | ON}] [next={label | 9-bit unsigned integer}] remote={label | 9-bit unsigned integer} cntl_val={29-bit unsigned integer} [data={25-bit unsigned integer] [hr_data= {7-bit unsigned integer} SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 950 Register A, B, R, S, or T (dashed for R, S, T) Remote CF Remote DF comp_mode Selects the comparison mode type to be used. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 951: Comparison Type Encoding Format

    Remote Data Field = Selected register + Immediate Data Field (including HR field); Remote Control Field = Immediate Control Field; Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 952 , where M is the desired denominator from Divisor = M · (Equation 31) and lr is the loop resolution prescale value. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 953 Data Field[31:0]=Data Field[31:0] - Reg T[31:0]; C = 1; else Data Field[31:0] = T[31:0] >> 1; /* T/2 */ Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 954 Generally, register B holds the angle values and register A holds the time values. Bit 0 of the conditional address field (C13) specifies whether the instruction is operating in angle or time operation mode. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 955 Cout_prv = Cout; (always executed) The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 956 Specifies the step increment to be added to the counter value each program resolution. These two bits provide the values for the SWF0 and SWF1 flags. The valid values are listed in Table 20-93. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 957: Step Width Encoding For Scnt

    Data field register = Data Field register - register T; Z = 1; Register A = Gap start value; Jump to Next Program Address; SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 958 (in, out, left, right), shift condition (shift on a defined clock edge on HET[0] or shift always), register for data storage (A, B, R, S or T), and the data pin. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 959: Shift Mode Encoding Format

    ON generates an interrupt if the Z flag is set. A value of OFF does not generate an interrupt. Default: OFF. data Specifies the 25-bit value for the data field. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 960 NOTE: The immediate data field evaluates all 0s or all 1s and is performed before the shift operation. The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 961 If the hr_lr bit is reset, the WCAP instruction will capture an HR time stamp into the data field on the selected edge condition. If the hr_lr bit is set, the HR capture is ignored. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 962: Event Encoding Format For Wcap

    Prv bit = Current Logic (Lx) value of selected pin; (always executed) The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 963 [D6:D0] if the specified capture condition is true on the selected pin. This instruction can be used with all pins, but the time stamp [D31:D7] has loop resolution only. SPNU503C – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 964: Event Encoding Format For Wcape

    Prv bit = Current Logic (Lx) value of selected pin; (always executed) The specific interrupt flag that is triggered depends on the address from which the instruction is executed, Section 20.2.7. High-End Timer (N2HET) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 965 ....................... 21.3 Use Cases ..................21.4 HTU Control Registers ............ 21.5 Double Control Packet Configuration Memory 1008 ....................... 21.6 Examples 1015 SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 966 Constant and post-increment addressing modes • 32- or 64-bit transactions • Programmable memory protection region • Parity protect control packet RAM • Extensive diagnostic functionality High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 967 HTU module. Figure 21-1. System Block Diagram RAM0 Master Slave RAM1 Port Port Peripheral Bus N2HET SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 968 Frame count =4 Frame 1 Frame 2 Frame 3 Frame 4 Element1 Element2 Element3 Element4 Element5 Element6 Element7 Element8 HTUREQ HTUREQ HTUREQ HTUREQ High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 969 ADDFM = 0 (Addressing Mode Main Memory = Post Increment). So there are in total 9 32-bit values in the buffer. It also assumes IFADDRx = 10h. "U" means uninitialized. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 970 CFTCTx CFTCTx full address full address CFADDRx CFADDRx buffer full flag buffer full flag BFINTFL BFINTFL High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 971 11 12 13 14 15 16 17 18 19 20 Memory View for DCP-1A/B Buffer 1A Buffer 1A Switch Buffer 1B SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 972 BFINTFL buffer location 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h busy bit frame counter CFTCTA full address CFADDRA High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 973: Cpena / Tmbx Priority Rules

    If two or more request lines are active, the request line with the lower number (specified in the request number field of the corresponding N2HET instruction) is serviced first. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 974 In dual buffer mode, the request lost detection works continuously, independent of the CP switches. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 975 Since enabling the quiet request should enable a proper request lost detection for DCP x, both N2HET instructions need to specify the same DCP x (reqnum=x). SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 976: Triggered Control Packets

    If the signal frequency would increase, then a wrong pair [22, 23] could be read, but this will be signaled by a request lost error since at least e2 falls into the RL period. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 977 COPE bit is 0, then the DCP x will be automatically disabled in the CPENA register. If a frame for this DCP x is ongoing during SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 978: Dcp Ram

    If a 1 is written to HTUEN during the initialization, then the HTUEN bit will be set but the HTU will not be enabled before the initialization completes. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 979: Field Addresses Of The Wcap, Ecnt, Pcnt Example

    PCNT block. When the PCNT condition is true, it will cause the generated HTU frame to perform three HTU element reads from the data fields of WCAP, ECNT, and PCNT. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 980: 32-Bit-Transfer Of Data Fields

    IHADDRCT = [DIR: Read HET and write to full address] [SIZE: 32 bit] [ADDMH: Increment HET address by 16 bytes] [ADDMF: Post increment full address mode] [Any transfer mode] High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 981: 64-Bit-Transfer Of Control Field And Data Fields

    For different applications, which have the transfer direction set for reading the buffer and writing to HET fields, the 64-bit transfer could be used to change the conditional addresses together with a new data field. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 982: Htu Control Registers

    Section 21.4.26 HTU MP0S Memory Protection 0 Start Address Register Section 21.4.27 HTU MP0E Memory Protection 0 End Address Register Section 21.4.28 High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 983: Global Control Register (Htu Gc) Field Descriptions

    • Wait for the HTURES bit to clear. • Configure the HTU registers and packets. • Set the HTUEN bit to begin operation. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 984: Control Packet Enable Register (Htu Cpena) Field Descriptions

    CPENA and the action defined by TMBx can contradict. The priority rules for this case are given in Table 21-1. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 985: Control Packet (Cp) Busy Register 0 (Htu Busy0) Field Descriptions

    CPU can poll the busy bit to determine when it is safe to read the buffer. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 986: Control Packet (Cp) Busy Register 1 (Htu Busy1) Field Descriptions

    Busy Flag for CP A of DCP 5 Reserved Reads return 0. Writes have no effect. BUSY5B Busy Flag for CP B of DCP 5 High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 987: Control Packet (Cp) Busy Register 3 (Htu Busy3) Field Descriptions

    32-bit register. It is also cleared when writing a 1 to ERRF. ERRF can be used to indicate if ERRETC and ERRCPN contain new unread data. 30-29 Reserved Reads return 0. Writes have no effect. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 988 CP. Note, that there can be a delay between the request and the start of the frame. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 989: Request Lost And Bus Error Control Register (Htu Rlbectrl) Field Descriptions

    The request lost interrupt is enabled for all DCPs. If bits are set in the RLOSTFL flag register at the time RLINTENA is (re-) enabled, then the according interrupt(s) will occur (in the order of the priority of the request lines). SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

  • Page 990: Buffer Full Interrupt Enable Set Register (Htu Bfints) Field Descriptions

    Writing to bit (2*x) disables the interrupt for CP A of DCP x. Writing to bit (2*x+1) disables the interrupt for CP B of DCP x. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 991 Interrupt of CP A (bit 2-x) of DCP x is mapped to interrupt line 1. Interrupt of CP B (bit 2*x+1) of DCP x is mapped to interrupt line 1. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 992 In order to read INTTYPE0 and CPOFF0 simultaneously, always read this register using word or half-word but not using byte accesses. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 993 In order to read INTTYPE1 and CPOFF1 simultaneously, always read this register using word or half-word but not using byte accesses. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 994 21-13). This is regardless of whether the switch is done by a write access to CPENA or by the auto-switch feature. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 995 Table 21-27 also apply for this situation. The software should use the procedures explained in the first note before setting HTUEN. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 996 • Reading BFINTFL will not clear the flags or • Reading INTOFFx will clear the corresponding flags or • Writing a 1 clears the corresponding flag. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 997 • Reading from INTOFFx in case of a BER interrupt clears the corresponding flag or • Writing a 1 clears the corresponding flag. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 998 0. The effective end address is rounded up to the nearest word end address, that is, 0x200 = 0x203. High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 999 This bit and all other bits of the DCTRL, WPR and WMR registers are reset by the test reset (nTRST) but not by the normal device reset. SPNU503C – March 2018 High-End Timer Transfer Unit (HTU) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
  • Page 1000 This register can only be programmed during debug mode. This register and all other bits of the DCTRL and WPR registers are reset by the test reset (nTRST) but not by the normal device reset. 1000 High-End Timer Transfer Unit (HTU) Module SPNU503C – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

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