Texas Instruments MSPM0G310x-Q1 Manual
Texas Instruments MSPM0G310x-Q1 Manual

Texas Instruments MSPM0G310x-Q1 Manual

Automotive mixed-signal microcontrollers with can-fd interface

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MSPM0G310x-Q1 Automotive Mixed-Signal Microcontrollers With CAN-FD Interface

1 Features

Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80MHz
Functional Safety Quality-Managed
Functional Safety Manual
available to aid in functional safety system
design
Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62V to 3.6V
Memories
– Up to 128KB of flash memory with built-in error
correction code (ECC)
– Up to 32KB of SRAM with hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4Msps
analog-to-digital converters (ADCs) with up to
17 external channels
14-bit effective resolution at 250ksps with
hardware averaging
– One general-purpose amplifier (GPAMP)
– Configurable 1.4V or 2.5V internal shared
voltage reference (VREF)
– Integrated temperature sensor
– Integrated supply monitor
Optimized low-power modes
– RUN: 101µA/MHz (CoreMark)
– SLEEP: 487µA at 4MHz
– STOP: 47µA at 32kHz
– STANDBY: 1.5µA with RTC and SRAM
retention
– SHUTDOWN: 80nA with IO wakeup capability
Intelligent digital peripherals
– 7-channel DMA controller
– Two 16-bit advanced control timers support
dead band insertion and fault handling
– Seven timers supporting up to 22 PWM
channels
One 16-bit general purpose timer
One 16-bit general purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit general-purpose timer
Two 16-bit advanced timers with deadband
– Two window-watchdog timers
– RTC with alarm and calendar mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
-M0+ CPU with memory
and
FMEDA
MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1
SLASF86B – OCTOBER 2023 – REVISED MAY 2024
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
2
– Two I
C interfaces supporting up to FM+
(1Mbit/s), SMBus, PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
Clock system
– Internal 4MHz to 32MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80MHz
– Internal 32kHz oscillator (LFOSC) with ±3%
accuracy
– External 4MHz to 48MHz crystal oscillator
(HFXT)
– External 32kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128- or 256-bit key
Flexible I/O features
– Up to 60 GPIOs
Two 5V-tolerant IOs
Two high-drive IOs with 20mA drive strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 64-pin LQFP
– 48-pin LQFP, VQFN
– 32-pin VQFN
– 32 and 28-pin VSSOP
– 20-pin VSSOP
Family members (also see
– MSPM0G3105: 32KB flash, 16KB RAM
– MSPM0G3106: 64KB flash, 32KB RAM
– MSPM0G3107: 128KB flash, 32KB RAM
Development kits and software (also see
and
Software)
LP-MSPM0G3507 LaunchPad
kit
– MSP Software Development Kit (SDK)
Automotive qualification
– AEC-Q100 Grade 1
– 32-pin and 48-pin QFNs with wettable flanks
option
Device
Comparison)
Tools
development

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Summary of Contents for Texas Instruments MSPM0G310x-Q1

  • Page 1: Features

    MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 SLASF86B – OCTOBER 2023 – REVISED MAY 2024 MSPM0G310x-Q1 Automotive Mixed-Signal Microcontrollers With CAN-FD Interface • Enhanced communication interfaces 1 Features – Four UART interfaces; one supports LIN, • Core IrDA, DALI, Smart Card, Manchester, and – Arm ®...
  • Page 2: Applications

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 3: Functional Block Diagram

    LFXIN, LFXOUT VDD, VSS HFXIN, HFXOUT VCORE, NRST PD1, CPU/DMA access ROSC PD1/PD0, CPU/DMA access CLK_OUT, FCC_IN PD0, CPU/DMA access Figure 4-1. MSPM0G310x Functional Block Diagram Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 4: Table Of Contents

    8.2 Operating Modes............10.8 Glossary..............66 8.3 Power Management Unit (PMU)....... 11 Revision History............8.4 Clock Module (CKM)..........46 12 Mechanical, Packaging, and Orderable 8.5 DMA................Information..............8.6 Events............... Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, Section For more information about the device name, see Section 10.2. 32- and 48 -pin VQFN package available with wettable flanks. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 6: Pin Configuration And Functions

    PA30 PA20 / SWCLK PA29 PB17 / A1_4 PA28 PB18 / A1_5 PB19 / A1_6 PA0 / FCC_IN Figure 6-2. 64-Pin PM (LQFP) (Top View) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 7 PA12 / FCC_IN PA4 / LFCLK_IN / LFXOUT PB16 PA5 / HFXIN / FCC_IN PB15 PA6 / HFCLK_IN / HFXOUT Figure 6-3. 48-Pin PT (LQFP) (Top View) Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 8 PA4 / LFCLK_IN / LFXOUT PA12 / FCC_IN PA5 / HFXIN / FCC_IN PB16 PA6 / HFCLK_IN / HFXOUT PB15 Thermal pad Figure 6-4. 48-Pin RGZ (VQFN) (Top View) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 9 PA14 / CLK_OUT / A0_12 PA13 PA7 / CLK_OUT PA12 / FCC_IN PA11 PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT Figure 6-6. 32-Pin DGS28(VSSOP) (Top View) Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 10 Figure 6-8. 20-Pin DGS20 (VSSOP) (Top View) Note For the full pin configuration and description of the functions for each package option, see Attributes Signal Descriptions. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 11: Pin Attributes

    CAN_TX [5] / TIMA0_C3 [6] / FCC_IN [7] Speed UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] / – High- PA13 – TIMG0_C1 [5] / CAN_RX [6] / TIMA0_C3N [7] Speed Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 12 UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / – – – – Standard TIMA1_C0 [8] Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 13 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] – – – Standard UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / PB26 – – – Standard TIMG6_C0 [5] / TIMA1_C0 [6] Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 14: Signal Descriptions

    ADC1 analog input 7 BSL_invoke Input pin used to invoke bootloader BSL (I BSLSCL – Default I C BSL clock BSLSDA – Default I C BSL data Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 15 General-purpose digital I/O PA10 General-purpose digital I/O with wake up from SHUTDOWN PA11 General-purpose digital I/O with wake up from SHUTDOWN PA12 – – General-purpose digital I/O Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 16 PB19 – – – – General-purpose digital I/O PB20 – – – – General-purpose digital I/O PB21 – – – – – General-purpose digital I/O Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 17 SPI0_CS3 SPI0 chip-select 3 SPI0_SCK SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI SPI0 controller in/peripheral out Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 18 General purpose timer 0 CCR1 capture input/ compare output TIMG6_C0 General purpose timer 6 CCR0 capture input/ compare output TIMG6_C1 General purpose timer 6 CCR1 capture input/ compare output Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 19 TIMA0_C0 – Advanced control timer 0 CCR0 capture input/ compare output TIMA0_C0N Advanced control timer 0 CCR0 capture input/ compare output (inverting) Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 20 (inverting) TIMA1_C0 Advanced control timer 1 CCR0 capture input/ compare output TIMA1_C0N – Advanced control timer 0 CCR3 capture input/ compare output (inverting) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 21 UART1_TX UART1 transmit data UART1_RX UART1 receive data UART1_CTS – UART1 "clear to send" flow control input UART1_RTS UART1 "request to send" flow control output Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 22: Connections For Unused Pins

    Section 9.1. Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx and PBx" unused pin connection guidelines. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 23: Specifications

    JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback...
  • Page 24: Recommended Operating Conditions

    Junction-to-board thermal resistance 13.0 °C/W θJB VQFN-32 (RHB) Ψ Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 13.0 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 25 Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 26: Supply Current Characteristics

    32kHz STOP2 ULPCLK=LFCLK STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, RTC enabled 32kHz µA LFCLK=LFXT, STOPCLKSTBY=1, STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, GPIOA enabled Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 27: Power Supply Ramp

    (1) (2) Rising 2.88 2.96 3.04 BOR3+ (1) (2) Brownout-reset voltage level 3 Falling 2.85 2.93 3.01 BOR3- STANDBY mode 2.80 2.92 3.02 BOR3, STBY Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 28: Flash Memory Characteristics

    Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links:...
  • Page 29: Timing Characteristics

    The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user program is executed. 7.9 Clock Specifications Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 30 The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 31 7.9.4 Low Frequency Crystal/Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Low frequency crystal oscillator (LFXT) LFXT frequency 32768 LFXT Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 32 Manual.Current consumption increases with higher RSEL and start up time is decreases with higher RSEL. The digital clock input (HFCLK_IN) accepts a logic level square wave clock. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 33: Digital Io

    -40°C ≤T ≤130°C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 34 VDD ≥ 1.71V, DRV = 0, CL= 20pF HDIO VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 35: Analog Mux Vboost

    = VREF = 2.5V ADC Wakeup Time Assumes internal reference is active wakeup Supply Monitor voltage divider (4)(6) ADC input channel: Supply Monitor -1.5 SupplyMon (VDD/3) accuracy Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 36 Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with V = VREF+ = VDD and V = VSS = 0V, external 1µF cap on VREF+ pin. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 37: Typical Connection Diagram

    BUFCONFIG = {0, 1}, No load µA VREF VREF output drive strength Drive strength supported on VREF+ device pin µA Drive VREF short circuit current Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 38: Gpamp

    Common mode rejection ratio, DC range CHOP = 0x1 f = 1kHz Input voltage noise density Noninverting, unity gain nV/√Hz f = 10kHz Input resistance 0.65 kΩ Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 39: I2C

    LOW period of the SCL clock High period of the SCL clock 0.26 HIGH Setup time for a repeated 0.26 SU,STA START Data hold time HD,DAT Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 40: Spi

    2.7 < VDD < 3.6V Peripheral mode with High speed IO SCK Duty Cycle Controller /2) - /2) + SCLK High or Low time SCLK_H/L Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 41 Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback...
  • Page 42: Uart

    UART BITCLK clock frequency(equals UART in Power Domain1 BITCLK baud rate in MBaud) BITCLK clock frequency(equals UART in Power Domain0 BITCLK baud rate in MBaud) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 43: Timx

    51.2 µs LAT256 20MHz 7.22 Emulation and Debug 7.22.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 44: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 45 Core Functions Flash SRAM UART3 SPI0, SPI1 Peripherals MCAN0 TIMA0, TIMA1 TIMG6, TIMG7 TIMG12 TIMG0, TIMG8 UART0, UART1, UART2 Peripherals I2C0, I2C1 GPIOA, GPIOB WWDT0, WWDT1 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 46: Power Management Unit (Pmu)

    MFPCLK: 4MHz fixed mid-frequency precision clock, available in RUN, SLEEP, and STOP modes • LFCLK: 32kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 47: Dma

    The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA, or the CPU). The event manager implements event transfer through a defined set Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback...
  • Page 48: Memory

    128KB-8B ECC Corrected 0x0000.0000 to 0x0000.0000 to 0x0000.0000 to 0x0000.7FF8 0x0000.FFF8 0x0001.FFF8 Code (Flash) 0x0040.0000 to 0x0040.0000 to 0x0040.0000 to ECC Uncorrected 0x0040.7FF8 0x0040.FFF8 0x0041.FFF8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 49 0x40082000 0x2000 TIMG0 0x40084000 0x2000 TIMG8 0x40090000 0x2000 0x40094000 0x2000 GPIO0 0x400A0000 0x2000 GPIO1 0x400A2000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 50 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 51: Flash Memory

    (devices with 32KB support 100,000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the technical reference manual. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 52: Sram

    – MCU supply voltage (VDD) – External reference supplied to the ADC through the VREF+ and VREF- pins • Operates in RUN, SLEEP, and STOP modes Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 53: Temperature Sensor

    The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: • Software selectable chopper stabilization Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 54: Trng

    – Programmable baud rate generation with oversampling by 16, 8 or 3 – Local Interconnect Network (LIN) mode support • Separated transmit and receive FIFOs support DAM data transfer Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 55: I2C

    Supports TI mode, Motorola mode and National Microwire format Only SPI signals on HSIO pins support data rate > 16Mbps; see the Pin Diagrams section for HSIO pins. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 56: Can-Fd

    Compensation for temperature drift (up to ± 240ppm) • RTC clock output to pin for calibration For more details, see the RTC chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 57: Timers (Timx)

    – – – – – – TIMG12 32-bit – – – – – – – TIMA0 16-bit 8-bit 8-bit – TIMA1 16-bit 8-bit 8-bit – Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 58: Device Analog Connections

    For more details, see the TIMx chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual. 8.26 Device Analog Connections Figure 8-1 shows the internal analog connection of the device Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 59: Input/Output Diagrams

    See the device-specific data sheet for detailed information on what features are supported for a specific pin. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 60: Serial Wire Debug Interface

    Table 8-12. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 61: Bootstrap Loader (Bsl)

    DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. Device DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0G3105 0xBB88 0x17 MSPM0G3106 0xBB88 0x17 MSPM0G3107 0xBB88 0x17 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 62: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4). Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 63: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 64: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 65: Tools And Software

    GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain. Arm GCC is supported by Code Composer Studio IDE (CCS). Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 66: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 67: Mechanical, Packaging, And Orderable Information

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback...
  • Page 68 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 69 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 70 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 71 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 72 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 73 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 74 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 75 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 76 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 77 ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 78 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 79 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 80 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 81 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 82 MSPM0G3107-Q1, MSPM0G3106-Q1, MSPM0G3105-Q1 www.ti.com SLASF86B – OCTOBER 2023 – REVISED MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: MSPM0G3107-Q1 MSPM0G3106-Q1 MSPM0G3105-Q1...
  • Page 83 DETAIL A A 20 TYPICAL 4226367/A 10/2020 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.
  • Page 84 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  • Page 85 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 86 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2024 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) M0G3107QPMRQ1 ACTIVE LQFP 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 M0G3107Q...
  • Page 87 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2024 Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Lead finish/Ball material - Orderable Devices may have multiple material finish options.
  • Page 88 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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