Table 2.5 Logic Operations Instructions; Table 2.6 Shift Instructions - Renesas H8S Series Hardware Manual

Table 2.5 Logic Operations Instructions
Size *
Instruction
AND B/W/L
OR B/W/L
XOR B/W/L
NOT B/W/L
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Size *
Instruction
SHAL B/W/L
SHAR
SHLL B/W/L
SHLR
ROTL B/W/L
ROTR
ROTXL B/W/L
ROTXR
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ Rd → Rd
Takes the one's complement of general register contents.
Function
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
Rev. 6.00 Mar 15, 2006 page 35 of 570
REJ09B0211-0600
Section 2 CPU