Pixel Data And Synchronization Signals Control - Analog Devices Advantiv ADV7604 Hardware Manual

Function
OP_CH_SEL[2:0]
110
111
PIXBUS_MSB_TO_LSB_REORDER, IO Map, Address 0x30, [4]
Function
PIXBUS_MSB_TO_
LSB_REORDER
0
1
Important: Unused pins of the pixel output for any available output format are driven with a low
signal.
5.4

Pixel Data and Synchronization Signals Control

• The polarity of the LLC and synchronization signals can be inverted, and the LLC,
synchronization signals, and the pixel data output can be tristated. Refer to the information on
the following controls:
•
INV_SYNC_OUT_POL
•
INV_F_POL
•
INV_VS_POL
•
INV_HS_POL
•
TRI_PIX
•
TRI_LLC
•
TRI_SYNCS
OP_SWAP_CB_CR, IO Map, Address 0x05, [0]
OP_SWAP_CB_CR
It caters for cases in which the data on channels B and C are swapped.
It is effective only if:
• CP is active
•
OP_FORMAT_SEL[7:0]
Note: It has no effect for 24-bit SDR modes and DDR modes
Function
OP_SWAP_CB_CR
0
1
Rev. F August 2010
Description
Reserved
Reserved
Description
Output bus goes from MSB to LSB
Output bus goes from LSB to MSB
swaps the order in which Cb and Cr are interleaved in the output data stream.
is set to a 4:2:2 compatible output mode
Description
Normal operation
Inverts the order of Cb and Cr in the interleaved data stream
60
ADV7604