ST STM32L4+ Series Reference Manual page 1535

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IWDG prescaler register (IWDG_PR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider

These bits are write access protected see

written by software to select the prescaler divider feeding the counter clock. PVU bit of the

IWDG status register (IWDG_SR)

Note: Reading this register returns the prescaler value from the V

000: divider /4

001: divider /8

010: divider /16

011: divider /32

100: divider /64

101: divider /128

110: divider /256

111: divider /256

value may not be up to date/valid if a write operation to this register is ongoing. For this

reason the value read from this register is valid only when the PVU bit in the

status register (IWDG_SR)

Section 44.3.5: Register access

must be reset in order to be able to change the prescaler

RM0432 Rev 6

Independent watchdog (IWDG)

protection. They are

voltage domain. This

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