ST STM32L4+ Series Reference Manual page 1524

Hide thumbs Also See for STM32L4+ Series:

Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only

LPTIM control register (LPTIM_CR)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 RSTARE: Reset after read enable

This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT

Bit 3 COUNTRST: Counter reset

This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous

reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes

place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be

different from APB clock).

Caution: COUNTRST must never be set to '1' by software before it is already cleared to '0' by

Bit 2 CNTSTRT: Timer start in Continuous mode

This bit is set by software and cleared by hardware.

In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode.

If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in

Continuous mode as soon as an external trigger is detected.

If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the

next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps

counting in Continuous mode.

This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.

Bit 1 SNGSTRT: LPTIM start in Single mode

This bit is set by software and cleared by hardware.

In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode.

If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in

single pulse mode as soon as an external trigger is detected.

If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the

following match between LPTIM_ARR and LPTIM_CNT registers.

This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.

Bit 0 ENABLE: LPTIM enable

The ENABLE bit is set and cleared by software.

0: LPTIM is disabled.

1: LPTIM is enabled

hardware. Software should consequently check that COUNTRST bit is already cleared to '0'

before attempting to set it to '1'.

RM0432 Rev 6

Need help?

Do you have a question about the STM32L4+ Series and is the answer not in the manual?