ST STM32L4+ Series Reference Manual page 1528

Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only
42.7.12 LPTIM register map
The following table summarizes the LPTIM registers.
Offset Register name
LPTIM_ISR
0x000
Reset value
LPTIM_ICR
0x004
Reset value
LPTIM_IER
0x008
Reset value
LPTIM_CFGR
0x00C
Reset value
LPTIM_CR
0x010
Reset value
LPTIM_CMP
0x014
Reset value
LPTIM_ARR
0x018
Reset value
LPTIM_CNT
0x01C
Reset value
LPTIM1_OR
0x020
Reset value
LPTIM2_OR
0x020
Reset value
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Table 309. LPTIM register map and reset values
0 0 0 0 0 0 0 0
RM0432 Rev 6
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
CMP[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
CNT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0432
0 0 0 0 0
0 0 0 0 0
0 0
0 0