ST STM32L4+ Series Reference Manual page 1529

RM0432 Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only
Table 309. LPTIM register map and reset values (continued)
Offset Register name
REP[7:0]
LPTIM_RCR
0x028
0 0 0 0 0 0 0 0
Reset value
1. If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 42.3: LPTIM
implementation.
Refer to Section 2.2 on page 91 for the register boundary addresses.
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