Summary of Contents for Texas Instruments TMDSEVM6678L EVM
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TMDSEVM6678L EVM Technical Reference Manual Version 2.01 Literature Number: SPRUH58 Revised March 2012 Document Copyright Publication Title: TMDSEVM6678L Technical Reference Manual All Rights Reserved. Reproduction, adaptation, or translation without prior written permission is prohibited, except as allowed under copyright laws. 1 ...
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EVALUATION BOARD / KIT / MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMER Not for Diagnostic Use: For Feasibility Evaluation Only in Laboratory/Development Environments The EVM may not be used for diagnostic purposes. This EVM is intended solely for evaluation and development purposes. It is not intended for use and may not be used as all, or part of an end equipment product. This EVM should be used solely by qualified engineers and technicians who are familiar with the risks associated with handling electrical and mechanical components, systems and subsystems. Your Obligations and Responsibilities Please consult the EVM documentation, including but not limited to any user guides, setup guides or getting started guides, and other warnings prior to using the EVM. Any use of the EVM outside of the specified operating range may cause danger to users and/or produce unintended results, inaccurate operation, and permanent damage to the EVM and associated electronics. You acknowledge and agree that: ...
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Preface About this Document This document is a Technical Reference Manual for the TMS320C6678 Evaluation Module (TMDSEVM6678L) designed and developed by Advantech Limited for Texas Instruments, Inc. Notational Conventions This document uses the following conventions: Program listings, program examples, and interactive displays are shown in a mono spaced font. Examples use bold for emphasis, and interactive displays use bold to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets. Unless the square brackets are in a bold typeface, do not enter the brackets themselves. Underlined, italicized non‐bold text in a command is used to mark place holder text that should be replaced by the appropriate value for the user’s configuration. 3 ...
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Trademarks The Texas Instruments logo and Texas Instruments are registered trademarks of Texas Instruments. Trademarks of Texas Instruments include: TI, XDS, Code Composer, Code Composer Studio, Probe Point, Code Explorer, DSP / BIOS, RTDX, Online DSP Lab, TMS320, TMS320C54x, TMS320C55x, TMS320C62x, TMS320C64x, TMS320C67x, TMS320C5000, and TMS320C6000. MS‐DOS, Windows, Windows XP, and Windows NT are trademarks of Microsoft Corporation. UNIX is a registered trademark of The Open Group in the United States and other countries. All other brand, product names, and service names are trademarks or registered trademarks of their respective companies or organizations. 4 ...
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Document Revision History Release Chapter Description of Change 1.00 All The First Release for draft 2.00 All The Second Release for Rev 1.0 production 2.01 All The Third Release for Rev 3.0 production Acronyms Acronym Description AMC or AdvancedMC Advanced Mezzanine Card CCS Code Composer Studio DDR3 Double Data Rate 3 Interface DSP Digital Signal Processor DTE Data Terminal Equipment ...
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Figure 5.2: Reset‐Full Switch/Trigger Boot Configuration Timing .......... 6 9 Figure 5.3: The SPI access form the TMS320C6678 to the FPGA (WRITE / high level) .... 7 2 Figure 5.4: The SPI access form the TMS320C6678 to the FPGA (WRITE) ....... 7 2 Figure 5.5: The SPI access form the TMS320C6678 to the FPGA (READ / high level).... 7 2 Figure 5.6: The SPI access form the TMS320C6678 to the FPGA (READ) ........ 7 3 Figure 5.7: The SPI access form the FPGA to the CDCE62005 (WRITE) ........ 7 3 Figure 5.8: The SPI access form the FPGA to the CDCE62005 (READ) ........ 7 3 9 ...
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List of Tables Table 2.1: TMS320C6678 Memory Map .................. 1 6 Table 3.1 : TMDSEVM6678L EVM Board Connectors .............. 2 9 Table 3.2 : XDS560v2 Power Connector pin out .............. 3 0 Table 3.3: AMC Edge Connector .................... 3 0 Table 3.4: UART Connector pin out .................. 3 2 Table 3.5: UART Path Select Connector pin out ............... 3 3 Table 3.6: DSP JTAG Connector pin out .................. 3 4 Table 3.7 : FAN1 Connector pin out .................. 3 5 Table 3.8 : The HyperLink Connector .................. 3 6 Table 3.9 : Ethernet Connector pin out .................. 3 7 Table 3.10 : PMBUS1 pin out .................... ...
1. Overview This chapter provides an overview of the TMDSEVM6678L along with the key features and block diagram. 1.1 Key Features 1.2 Functional Overview 1.3 Basic Operation 1.4 Configuration Switch Settings 1.5 Power Supply 1.1 Key Features The TMDSEVM6678L is a high performance, cost‐efficient, standalone development platform that enables users to evaluate and develop applications for the Texas Instruments’ TMS320C6678 Digital Signal Processor (DSP). The Evaluation Module (EVM) also serves as a hardware reference design platform for the TMS320C6678 DSP. The EVM’s form‐factor is equivalent to a single‐wide PICMG® AMC.0 R2.0 AdvancedMC module. Schematics, code examples and application notes are available to ease the hardware development process and to reduce the time to market. The key features of the TMDSEVM6678L EVM are: Texas Instruments' multi‐core DSP – TMS320C6678 512 Mbytes of DDR3‐1333 Memory 64 Mbytes of NAND Flash 16MB SPI NOR FLASH Two Gigabit Ethernet ports supporting 10/100/1000 Mbps data‐rate – one on AMC connector and one RJ‐45 connector 170 pin B+ style AMC Interface containing SRIO, PCIe, Gigabit Ethernet and TDM High Performance connector for HyperLink 128K‐byte I2C EEPROM for booting 2 User LEDs, 5 Banks of DIP Switches and 4 Software‐controlled LEDs RS232 Serial interface on 3‐Pin header or UART over mini‐USB connector EMIF, Timer, SPI, UART on 80‐pin expansion header On‐Board XDS100 type Emulation using High‐speed USB 2.0 interface TI 60‐Pin JTAG header to support all external emulator types Module Management Controller (MMC) for Intelligent Platform Management Interface (IPMI) 11 ...
Optional XDS560v2 System Trace Emulation Mezzanine Card Powered by DC power‐brick adaptor (12V/3.0A) or AMC Carrier backplane PICMG® AMC.0 R2.0 single width, full height AdvancedMC module 1.2 Functional Overview The TMS320C66x™ DSPs (including the TMS320C6678 device) are the highest‐performance fixed / floating‐point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6678 device is based on the third‐generation high‐performance, advanced VelociTI™ very‐long‐instruction‐word (VLIW) architecture developed by Texas Instruments (TI), designed specifically for high density wireline / wireless media gateway infrastructure. It is an ideal solution for IP border gateways, video transcoding and translation, video‐server and intelligent voice and video recognition applications. The C66x devices are backward code‐compatible from previous devices that are part of the C6000™ DSP platform. ...
facilitate application software development on TI's high performance and multicore DSPs. The MCSDK also includes an out‐of‐box demonstration; see the "MCSDK Getting Started Guide". To start operating the board, follow instructions in the Quick Start Guide. This guide provides instruction for proper connections and configuration for running the POST and OOB Demos. After completing the POST and OOB Demos, proceed with installing CCS and the EVM support files by following the instructions on the DVD. This process will install all the necessary development tools, drivers and documentation. After the installation has completed, follow the steps below to run Code Composer Studio. 1. Power‐on the board using the power brick adaptor (12V/3.0A) supplied along with this EVM or inserting this EVM board into a MicroTCA chassis or AMC carrier backplane. 2. Connect USB cable from host PC to EVM board. 3. Launch Code Composer Studio from host PC by double clicking on its icon on the PC desktop. Detailed information about the EVM including examples and reference materials are available in the DVD included with this EVM kit. 80‐pin Expansion Header HyperLink SBW_MMC PMBUS1 ...
1.5 Power Supply The TMDSEVM6678L can be powered from a single +12V / 3.0A DC (36W) external power supply connected to the DC power jack (DC_IN1). Internally, +12V input is converted into required voltage levels using local DC‐DC converters. • CVDD (+0.90V~+1.05V) used for the DSP Core logic • +1.0V is used for DSP internal memory and HyperLink/SRIO/SGMII/PCIe SERDES termination of DSP • +1.5V is used for DDR3 buffers of DSP, HyperLink/SRIO/SGMII/PCIe SERDES regulators in DSP and DDR3 DRAM chips • +1.8V is used for DSP PLLs, DSP LVCMOS I/Os and FPGA I/Os driving the DSP • +2.5V is used for Gigabit Ethernet PHY core • +1.2V is used for FPGA core and Gigabit Ethernet PHY core • +3.3V is used for FPGA I/Os • +5V and +3.3V is used to power optional XDS560v2 mezzanine card • The DC power jack connector is a 2.5mm barrel‐type plug with center‐tip as positive polarity The TMDSEVM6678L can also draw power from the AMC edge connector (AMC1). If the board is inserted into a PICMG® MicroTCA.0 R1.0 compliant system chassis or AMC Carrier ...
standard TI DSP emulators. An adapter will be required for use with some emulators. The on‐board embedded JTAG emulator is the default connection to the DSP. However when an external emulator is connected to EVM, the board circuitry switches automatically to give emulation control to the external emulator. When the on‐board emulator and external emulator both are connected at the same time, the external emulator has priority and the on‐board emulator is disconnected from the DSP. The third way of accessing the DSP is through the JTAG port on the AMC edge connector, users can connect the DSP through the AMC backplane if they don’t use the XDS100 on‐board emulator and the 60‐pin header with the external emulator. The JTAG interface among the DSP, on‐board emulator, external emulator and the AMC edge connector is shown in the below figure. EMU_DETz EMU_DET PIN JTAG High‐Speed EMU1 JTAG +1.8V JTAG EMU[0..1] +1.8V SWITCH EMU[2..18] JTAG JTAG (TS3L301) High‐Speed Level Shifter +1.8V...
is driven into the clock generation device rather than using the local crystal. For the timing synchronization on the HyperLink SERDES, a common 25MHz timing source is fed from the AMC edge finger to the clock generator, CLK2, that drives a 100MHz source clock to the CLK3 for the MCM_CLK input on the DSP. It is supplied on the AMC connector at the TCLKB input. SEL (Controlled by FCLK: 100MHz PCIe_CLKp/n ( from PCIe_CLKp/n 100.00MHz CDCE62005 312.50MHz MCM_CLKp/n CLK3 312.50MHz PRI_RE SRIO_SGMII_CLKp/n SEC_RE 100.00MHz PA_SS_CLKp/n AUXIN TMS320C667 100.00MHz CDCE62005 Support common HyperLink timing at...
a SPI ROM for boot. The SPI module on TMS320C6678 is supported only in Master mode. The NOR FLASH attached to CS0z on the TMS320C6678 is a NUMONYX N25Q128A21. This NOR FLASH size is 16MB. It can contain demonstration programs such as POST or the OOB demonstration. The CS1z of the SPI is used by the DSP to access registers within the FPGA. 2.6 FPGA The FPGA (Xilinx XC3S200AN) controls the reset mechanism of the DSP and provides boot mode and boot configuration data to the DSP through SW3, SW4, SW5, SW6 and SW9. FPGA also provides the transformation of TDM Frame Sync and Clock between AMC connector and the DSP. The FPGA also supports 4 user LEDs and 1 user switch through control registers. ...
2.7 Gigabit Ethernet Connections The TMDSEVM6678L provides connectivity for both SGMII Gigabit Ethernet ports on the EVM. These are shown in figure below: TMS320C6678 SGMII_0 Port0 (EMAC0) Marvell SGMII_1 SGMII RJ‐4 (EMAC1) Level‐Shifter 88E1111 +1.8V +2.5V LAN1 MDIO MDIO Figure 2.4: TMDSEVM6678L EVM Ethernet Routing The Ethernet PHY (PHY1) is connected to DSP EMAC1 to provide a copper interface and routed ...
2.9 DDR3 External Memory Interface The TMS20C6678 DDR3 interface connects to four 2Gbit (128Mega x 16) DDR3 1333 devices on Rev 3.0 EVM and 1Gbit (64Mega X 16) DDR3 devices on all EVMs through Rev 2.0A. This configuration allows the use of both “narrow (16‐bit)”, “normal (32‐bit)”, and “wide (64‐bit)” modes of the DDR3 EMIF. SAMSUNG DDR3 K4B2G1646C‐HCH9 SDRAMs (128Mx16; 667MHz) are used on the DDR3 EMIF on Rev 3.0 EVM and the K4B2G1646C‐HCH9 chips (64Mx16; 667MHz) are installed on Rev 2.0A and earlier revision EVMs. The figure 2.6 illustrates the implementation for the DDR3 SDRAM memory on Rev 3.0 EVM. Please note that the size of DDR3 memory is 512MB with four 1Gb chips on Rev 2.0A and earlier EVMs instead. TMS320C6678 DDR3 EMIF DDR3 SDRAM 667MHz 2G‐bit Figure 2.6: TMDSEVM6678L EVM SDRAM 2.10 16‐bit Asynchronous External Memory Interface (EMIF‐16) The TMS20C6678 EMIF‐16 interface connects to one 512Mbit (64MB) NAND flash device and 80‐pin expansion header (TEST_PH1) on the TMDSEVM6678L EVM. The EMIF16 module provides an interface between DSP and asynchronous external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide (literature number SPRUGZ3). NUMONYX NAND512R3A2d NAND flash (64MB) is used on the EMIF‐16. ...
TMS320C6678 EMIF‐16 D0‐D7 A0‐A23 D0‐D15 NAND CE1z / Flas 64MB 80‐pin Expansion CE0z Figure 2.7: TMDSEVM6678L EVM EMIF‐16 connections 2.11 HyperLink Interface The TMS320C6678 provides the HyperLink bus for companion chip/die interfaces. This is a four lane SerDes interface designed to operate at 12.5 Gbps per lane. The interface is used to connect with external accelerators. The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2‐wire output buses and two 2‐wire input buses. Each 2‐wire bus includes a data signal and a clock signal. ...
2.12 PCIe Interface The 2 lane PCI express (PCIe) interface on TMDSEVM6678L provides a connection between the DSP and AMC edge connector. The PCI Express interface provides low pin count, high reliability, and high‐speed data transfer at rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide (literature number SPRUGS6). The TMDSEVM6678L provides the PCIe connectivity to AMC backplane on the EVM, this is shown in figure 2.9. TMS320C6678 Edge Connector PCIe[0:1] PCIe Port4 One Port / Port5 Two Lanes Figure 2.9: TMDSEVM6678L EVM PCIE Port Connections 2.13 Telecom Serial Interface Port (TSIP) The telecom serial interface port (TSIP) module provides a glueless interface to common telecom ...
TMS320C6678 +1.8V I/O +3.3V I/O TSIP0/1_TX3/RX1 Level TSIP0/1_TX1/RX3 TSIP0 / Edge Shift TSIP0/1_TX2/RX0 Connector TSIP1 TSIP0/1_TX0/RX2 Figure 2.10: TMDSEVM6678L EVM TSIP connections 2.14 UART Interface A serial port is provided for UART communication by TMS320C6678. This serial port can be accessed either through USB connector (USB1) or through 3‐pin (Tx, Rx and Gnd) serial port header (COM1). The selection can be made through UART Route Select shunt‐post COM_SEL1 as follows: • UART over mini‐USB Connector ‐ Shunts installed over COM_SEL1.3‐ COM_SEL1.1 and COM_SEL1.4 ‐ COM_SEL1.2 (Default) • UART over 3‐Pin Header (COM1) ‐ Shunts installed over COM_SEL1.3‐ COM_SEL1.5 and COM_SEL1.4 –COM_SEL1.6 TMS320C6678 USB1 COM_SEL1 USB‐JTAG Mini‐USB Console port FT2232HL UART UART UART +1.8V +3.3V COM1 RS232 RS232 MAX3221EAE Level Shifter...
The MMC will communicate with MicroTCA Carrier Hub (MCH) over IPMB (Intelligent Platform Management Bus) when inserted into an AMC slot of a PICMG® MTCA.0 R1.0 compliant chassis. The primary purpose of the MMC is to provide necessary information to MCH, to enable the payload power to TMDSEVM6678L EVM when it is inserted into the MicroTCA chassis. ...
3. TMDSEVM6678L Board Physical Specifications This chapter describes the physical layout of the TMDSEVM6678L board and its connectors, switches and test points. It contains: 3.1 Board Layout 3.2 Connector Index 3.3 Switches 3.4 Test Points 3.5 System LEDs 3.1 Board Layout The TMDSEVM6678L board dimension is 7.11” x 2.89” (180.6mm x 73.5mm). It is a 12‐layer board and powered through connector DC_IN1. Figure 3‐1 and 3‐2 shows assembly layout of the TMDSEVM6678L EVM Board. Figure 3.1: TMDSEVM6678L EVM Board Assembly Layout – TOP view 28 ...
Figure 3.2: TMDSEVM6678L EVM Board layout – Bottom view 3.2 Connector Index The TMDSEVM6678L Board has several connectors which provide access to various interfaces on the board. Table 3.1 : TMDSEVM6678L EVM Board Connectors Connector Pins Function 560V2_PWR1 8 XDS560v2 Mezzanine Power Connector AMC1 170 AMC Edge Connector COM1 3 UART 3‐Pin Connector COM_SEL1 6 UART Route Select Jumper DC_IN1 3 DC Power Input Jack Connector EMU1 60 TI 60‐Pin DSP JTAG Connector FAN1 3 FAN connector for +12V DC FAN HyperLink1 36 HyperLink connector for companion chip/die interface LAN1 12 Gigabit Ethernet RJ‐45 Connector PMBUS1 5 ...
3.2.1 560V2_PWR1, XDS560v2 Mezzanine Power Connector 560V2_PWR1 is an 8‐pin power connector for XDS560v2 mezzanine emulator board. The pin out for the connector is shown in the figure below: Table 3.2 : XDS560v2 Power Connector pin out Pin # Signal Name 1 +5VSupply 2 +5VSupply 3 XDS560V2_EN 4 Ground 5 +3.3VSupply 6 +3.3VSupply 7 Ground 8 Ground 3.2.2 AMC1, AMC Edge Connector The AMC card edge connector plugs into an AMC compatible carrier board and provides 4 ...
• UART over USB Connector (Default): Shunts installed over COM_SEL1.3‐COM_SEL1.1 and COM_SEL1.4‐COM_SEL1.2 • UART over 3‐Pin Header LAN1‐Shunts installed over COM_SEL1.3‐COM_SEL1.5 and COM_SEL1.4‐COM_SEL1.6 The pin out for the connector is shown in the table and figure below: Table 3.5: UART Path Select Connector pin out Pin # Signal Name Pin # Signal Name FT2232H (USB Chip) FT2232H (USB Chip) 1 2 Transmit Receive 3 UART Transmit 4 UART Receive 5 MAX3221 Transmit 6 MAX3221 Receive ...
Table 3.7 : FAN1 Connector pin out Pin # Signal Name 1 GNG 2 +12Vdc 3 NC 3.2.8 HyperLink1, HyperLink Connector The EVM provides a HyperLink connection by a mini‐SAS HD+ 4i connector. The connector contains 8 SERDES pairs and 4 sideband sets to carry full HyperLink signals. The connector is shown in Figure 3.3. and its pin out is shown in Table 3.8. This connector is the Molex iPass+HD connector 76867‐0011. The Molex cable 1110670200 can be used to connect two EVMs together. D1 C1 B1 A1 Figure 3.4 : The HyperLink Connector 35 ...
3.2.9 LAN1, Ethernet Connector LAN1 is a Gigabit RJ45 Ethernet connector with integrated magnetics. It is driven by Marvell Gigabit Ethernet transceiver 88E1111. The connections are shown in the table below: Table 3.9 : Ethernet Connector pin out Pin # Signal Name 1 Center Tap2 2 MD2‐ 3 MD2+ 4 MD1‐ 5 MD1+ 6 Center Tap1 7 Center Tap3 8 MD3+ 9 MD3‐ 10 MD0‐ 11 MD0+ ...
Table 3.10 : PMBUS1 pin out Pin # Signal Name 1 PMBUS_CLK 2 PMBUS_DAT 3 PMBUS_ALT 4 PMBUS_CTL 5 GND 3.2.11 TAP_FPGA1, FPGA JTAG Connector (For Factory Use Only) TAP_FPGA1 is an 8‐pin JTAG connector for the FPGA programming and the PHY boundary test of the factory only. The pin out for the connector is shown in the figure below: Table 3.11 : FPGA JTAG Connector pin out Pin # Signal Name ...
Boundary Scan Diagram TAP_FPGA1 TDO TMS/TCK/TRSTn TDO TDI Gigabit PHY FPGA (88E1111) XC3S200AN JTAG JTAG Figure 3.5 : TAP_FPGA1 function diagram 3.2.12 SBW_MMC1, MSP430 SpyBiWire Connector (For Factory Use Only) SBW_MMC1 is a 4‐pin SpyBiWire connector for IPMI software loading into MSP430. The TMDSEVM6678L are supplied with IPMI software already loaded into MSP430. The pin out for the connector is shown in the figure below: Table 3.12 : MSP430 JTAG Connector pin out Pin # Signal Name 1 2 VCC3V3_MP 3 MMC_SBWTDIO 4 MMC_SBWTCK 3.2.13 TEST_PH1, Expansion Header (EMIF‐16, SPI, GPIO, Timer I/O, I2C, and UART) TEST_PH1 is an expansion header for several interfaces on the DSP. They are 16‐bit EMIF, SPI, GPIO, Timer, I2C, and UART. The signal connections to the test header are as shown in a table below: ...
3.2.14 USB1, Mini‐USB Connector USB1 is a 5‐pin Mini‐USB connector to connect Code Composer Studio with TMS320C6678 DSP using XDS100 type on‐board emulation circuitry. Below table shows the pin outs of the Mini‐USB connector. Table 3.14 : Mini‐USB Connector pin out Pin # Signal Name 1 VBUS 2 USB D‐ 3 USB D+ 4 ID (NC) 5 Ground 3.3 DIP and Pushbutton Switches The TMDSEVM6678L has 3 push button switches and five sliding actuator DIP switches. The RST_FULL1, RST_COLD1, and RST_WARM1 are push button switches while SW3, SW4, SW5, SW6 and SW9 are DIP switches. The function of each of the switches is listed in the table below: Table 3.15 : TMDSEVM6678L EVM Board Switches Switch Function RST_FULL1 Full Reset Event ...
3.3.2 RST_COLD1, Cold Reset The button is reserved for future use. 3.3.3 RST_WARM1, Warm Reset Pressing the RST_WARM1 button switch will issue a RESET# to TMS320C6678 by the FPGA. The FPGA will assert the RESET# signal to the DSP and the DSP will execute either a HARD or SOFT reset by the configuration in the RSCFG register in PLLCTL. Note: Users may refer to the TMS320C6678 Data Manual to check the difference between assertion of DSP RESET# and the other reset signals. 3.3.4 SW3, SW4, SW5, and SW6, DSP boot mode and Configuration SW3, SW4, SW5, and SW6 are 4‐position DIP switches, which are used for DSP ENDIAN, Boot Device, Boot Configuration, and PCI Express subsystem configuration. For the details about the DSP Boot modes and their configuration, please refer to the TMS320C6678 Data Manual. The diagram of the default setting on these switches is shown below: SW3 OFF (0x1b) 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 Logic High ON (0x0b) Logic Low...
Table 3.16 : SW3‐SW6, DSP Configuration Switch Switch Description Default Value Function (HUA Demo) SW3[1] LENDIAN 1 (OFF) Device Endian mode (LENDIAN). 0 = Device operates in big Endian mode 1 = Device operates in little Endian mode SW3[4:2] Boot Device / 101b Boot Device 000b = EMIF16 and Emulation Boot Boot Mode (OFF,ON,OFF) 001b = Serial Rapid I/O [2:0] 010b = SGMII (PASSCLK rate same as CORECLK rate) 011b = SGMII (PASSCLK rate same as SGMIICLK rate) 100b = PCI Express 101b = I2C 110b = SPI 111b = HyperLink SW5[1] Parameter 00000b These 5 bits are the Parameter Index Index [4:0] / when I2C is the boot device. They have SW4[4:1] (ON,ON,ON, other definitions for other boot devices. Boot Mode ON,ON) ...
3.3.4 SW9, DSP PCIESS Enable and User Defined Switch Configuration SW9 is a 2‐position DIP switch. The first position is used for enabling the PCI Express Subsystem within the DSP. The second position is undefined by hardware and available for application software use. A diagram of the SW9 switch (with factory default settings) is shown below: ON (0x0b) Logic Low OFF (0x1b) Logic High ...
3.4 Test Points The TMDSEVM6678L EVM Board has 26 test points. The position of each test point is shown in the figures below: TP13 / TP14 TP40 / TP41 TP42 / TP43 TP33 / TP32 TP4 TP16 TP10 TP19 TP28 TP29 TP20 TP18 TP11 TP36 / TP37 TP22 TP27 TP26 TP21 TP24 TP30 TP25 Figure 3.8 : TMDSEVM6678L test points on top side TP17 TP8 / TP9 / TP7 TP12 TP5 TP6 TP15 Figure 3.9 : TMDSEVM6678L test points on the bottom side 45 ...
3.5 System LEDs The TMDSEVM6678L board has seven LEDs. Their positions on the board are indicated in figure 3.7. The description of each LED is listed in table below: Table 3.19 : TMDSEVM6678LTEEVM Board LEDs LED# Color Description Failure and Out of service status in AMC chassis Blue Hot Swap status in AMC chassis SYSPG_D1 Green All Power rails are stable on AMC FPGA_D1‐ Blue Debug LEDs. FPGA_D4 FPGA_D1‐D4 SYSPG_D1 Figure 3.10 : TMDSEVM6678L EVM Board LEDs 47 ...
4. System Power Requirements This chapter describes the power design of the TMDSEVM6678L board. It contains: 4.1 Power Requirements 4.2 Power Supply Distribution 4.3 Power Supply Boot Sequence 4.1 Power Requirements Note that the power estimates stated in this section are maximum limits used in the design of the EVM. They have margin added to allow the EVM to support early silicon samples that normally have higher power consumption than eventual production units. The maximum EVM power requirements are estimated to be: • EVM FPGA – 0.65W; • DSP Cooling Fans – 1.2W (+12Vdc/0.1A); • Clock Generators & clock sources – 3.30W; • DSP – 14.90W;[worse case] Core supplies: 13.0W; Peripheral supplies: 1.90W; • DDR3 – 2.63W; 5 SDRAMs to support 64‐bit with ECC of the DSP • Misc – 0.33W; • USB – 0.84W; • SGMII PHY – 1.14W; EVM board total: 31.2W; The selected AC/DC 12V adapter should be rated for a minimum of 36 Watts. The power planes in TMDSEVM6678L are identified in the following table: 48 ...
Device Net name Voltage Description Input 3.3V_MP_AMC +3.3V Management Power for MMC VCC12 +12V Payload Power to AMC Management VCC3V3_AUX +3.3V 3.3V Power Rail for all support devices on EVM VCC1V2 +1.2V 1.2V Power Rail for all support devices on EVM VCC1V8_AUX +1.8V 1.8V Power Rail for all support devices on EVM TMS320C6678 CVDD +0.9V~1.05V DSP Core Power VCC1V0 +1.0V DSP Fixed Core Power VCC1V8 +1.8V DSP I/O power VCC1V5 ...
by explanations of critical component selection: CVDD (AVS core power for TMS320C6678) VCC1V0 (1.0V fixed core power for TMS320C6678) VCC3V3_AUX (3.3V power for peripherals) VCC1V5 (1.5V DDR3 power for TMS320C6678 and DDR3 memories) VCC5 (5.0V power for the XDS520V2 mezzanine card) The CVDD and VCC1V0 power rails are regulated by TI Smart‐Reflex controller UCD9222 and the dual synchronous‐buck power driver UCD7242 to supply DSP AVS core and CVDD1 core power. The VCC3V3_AUX and VCC1V5 power rails are regulated by two TI 6A Synchronous Step Down SWIFT™ Converters, TPS54620, to supply the peripherals and other power sources and the DSP DDR3 EMIF and DDR3 memory chips respectively. The VCC5 power rail is regulated by TI 2A Step Down SWIFT™ DC/DC Converter, TPS54231, to supply the power of the XDS560V2 mezzanine card on TMDSEVM6678L. The high level diagrams and output components are shown in figure 4.2, figure 4.3, figure 4.4, and figure 4.5 as well as choosing the proper inductors and buck capacitors. 0.47uH VID PWM1 6.3V 220uFx2 47uFx2 fr. 330uFx3 6.3V PGND1 VCC1V0 UCD922 UCD724 0.47uH 330uFx3 220uFx2 47uFx2 Fixed PWM2 6.3V 6.3V PGND2 Figure 4.2: The CVDD and VCC1V0 (CVDD1) power design on TMDSEVM6678L EVM ...
VCC5 22uH 2.8A TPS54231D 100uF B340A 6.3V Output capacitor Inductor Calculation (KIND=0.3) L = ((Vin(max) ‐ Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw)) L = ((12.6 ‐ 5)/1 * Kind) * (5 / (12.7 * 570K)) L = ((7.6/ 0.3) * (5 / (7239K)) Cout=1/( 2 * 3.14 * 5 * 25K) L = (25.3) * Cout=1.3 L = Reference Reference Inductor 22uH Figure 4.5: The VCC5 power design on TMDSEVM6678L EVM 4.3 The Power Supply Boot Sequence Specific power supply and clock timing sequences are identified below. The TMS320C6678 DSP requires specific power up and power down sequencing. Figure 4.2 and Figure 4.3 illustrate the proper boot up and down sequence. Table 4.3 provides specific timing details for Figure 4.6 and Figure 4.7. Refer to the TMS320C6678 DSP Data Manual for confirmation of specific sequencing and timing requirements. Step Power rails Timing Descriptions Power‐Up 1 VCC12 , ...
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3 CVDD 5mS Enable the CVDD and VCC1V0, (DSP AVS core power) the UCD9222 power rail#1 is for CVDD and go first after both of VCC5 and VCC2V5 are stable for 5mS. 4 VCC1V0 5mS Turn on VCC1V0, the UCD222 (DSP CVDD1 fixed core power) power rail#2. The VCC1V0 will start the regulating power rail after enable it after 5mS, the start‐delay time is set by the UCD9222 configuration file. 5 VCC1V8 5mS Turn on VCC1V8 after VCC1V0 (DSP IO power) stable for 5mS. 6 CDCE62005#2/#3 initiations 5mS Unlock the 1.8V outputs and FPGA 1.8V outputs initiate the CDCE62005s after VCC1V8 stable for 5mS. De‐asserted CDCE62005 power down pins (PD#), initial the CDCE62005s. 7 ...
12 DSP GPIO pins for boot 1mS Release the DSP GPIO pins after configurations RESETFULLz de‐asserted for 1mS Power‐Down 13 RESETFULLz 0mS If there is any power failure PORz events or the AMC payload power off, the FPGA will assert the RESETFULLz and PORz signals to the DSP. 14 FPGA 1.8V outputs 5mS Locked 1.8V output pins on the CDCE62005 PD# pins FPGA and pull the CDCE62005 PD# pins to low to disable DSP clocks. 15 CVDD 0mS Turn off all main power rails. VCC1V0 VCC1V8 VCC1V5 VCC0V75 VCC2V5 ICS557‐08 PD# and OE# Table 4.3: The power‐up and down timing on the TMDSEVM6678L 56 ...
. TMDSEVM6678L FPGA FUNCTIONAL DESCRIPTION This chapter contains, 5.1 FPGA overview 5.2 FPGA signals description 5.3 Sequence of operation 5.4 Reset definition 5.5 SPI protocol 5.6 CDCE62005 Programming Descriptions 5.7 FPGA Configuration Registers 5.1 FPGA overview The FPGA (Xilinx XC3S200AN) controls the EVM power sequencing, reset mechanism, DSP boot mode configuration and clock initialization. The FPGA also provides the transformation of TDM Frame Synchronization signal and Reference Clock between the AMC connector and the DSP. The FPGA also supports 4 user LEDs and 1 user switch through control registers. All the FPGA registers are accessible by the TMS320C6678 DSP. The key features of the TMDSEVM6678L EVM FPGA are: TMDSEVM6678L EVM Power Sequence Control TMDSEVM6678L EVM Reset Mechanism Control TMDSEVM6678L EVM Clock Generator Initialization and Control TMS320C6678 DSP SPI Interface for Accessing the FPGA Configurable Registers Provides Shadow Registers for TMS320C6678 DSP to Access the Clock Generator Configurations Registers Provides Shadow Registers for TMS320C6678 DSP to Access the UCD9222 Devices via the PM Bus (RFU) Provides TMS320C6678 DSP Boot Mode Configuration switch settings to DSP MMC Reset Events Initiation Interface Provides the transformation of TDM Frame Synchronization and Reference Clock between AMC and DSP 59 ...
Provide Ethernet PHY Interrupt(RFU) and Reset Control Interface Provides support for Reset Buttons, User Switches and Debug LEDs 5.2 FPGA signals description This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. Throughout this manual, a ‘#’ or ‘Z’ will be used at the end of a signal name to indicate that the active or asserted state occurs when the signal is at a low voltage level. The following notations are used to describe the signal and type. I Input pin O Output pin I/O Bi‐directional pin Differential Differential Pair pins PU Internal Pull‐Up . Table 5.1 : TMDSEVM6678L EVM FPGA Pin Description Pin Name IO Type Description MMC Control : MMC_DETECT# I MMC Detection on the insertion to an AMC PU Chassis : This signal is an insertion indication from the MMC. The MMC will drive logic low state when the EVM module is inserted into an AMC chassis. MMC_RESETSTAT# O RESETSTAT# state to MMC : The FPGA will drive the same status of the DSP RESETSTAT# to the MMC via this signal. MMC_POR_IN_AMC# I MMC POR Request : This signal is used by the ...
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Pin Name IO Type Description Power Sequences Control : VCC5_PGOOD I 5V Voltage Power Good Indication : This signal indicates the 5V power is valid. VCC2P5_PGOOD I 2.5V Voltage Power Good Indication : This signal indicates the 2.5V power is valid. VCC3_AUX_PGOOD I 3.3V Auxiliary Voltage Power Good Indication : This signal indicates the 3.3V auxiliary power is valid. VCC0P75_PGOOD I 0.75V Voltage Power Good Indication : This signal indicates the 0.75V power is valid. VCC1P5_PGOOD I 1.5V Voltage Power Good Indication : This signal indicates the 1.5V power is valid. VCC1P8_PGOOD I 1.8V Voltage Power Good Indication : This signal indicates the 1.8V power is valid. SYS_PGOOD O System Power Good Indication : This signal is indicated by the FPGA to the system when all the power supplies are valid. VCC1P8_EN1 O 1.8V Voltage Power Supply Enable : VCC1P8_EN1 is for 1.8V power plane control. VCC0P75_EN O ...
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Pin Name IO Type Description CLOCK[2:3]_SSPSO I SPI Serial Data MISO : This signal is connected PU to the TI CLOCK Generators MISO CDCE62005 pin. This signal is used for the serial data transfers from the slave ( ) output to CDCE62005 the master (FPGA) input. REFCLK[2:3]_PD# O TI CDCE62005 CLOCK Generator Power Down : The power down pins each place the respective CDCE62005 into the power down state forcing the differential clock output into the high‐impedance state. UCD9222 Interface : UCD9222_PG1 I UCD9222 Power Good Indication for CVDD DSP Core Power : This signal indicates the CVDD DSP core power is valid. UCD9222_ENA1 O UCD9222 Enable for CVDD DSP Core Power : UCD9222_ENA1 is for CVDD DSP core power plane control. UCD9222_PG2 I UCD9222 Power Good Indication for VCC1V0 DSP Core Power : This signal indicates the VCC1V0 DSP core power is valid. UCD9222_ENA2 ...
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Pin Name IO Type Description PHY_RST# O Reset to 88E1111 PHY : This signal is used to reset the 88E1111 PHY device. The PHY_RST# will be asserted during the active DSP_PORZ or DSP_RESETFULLZ period. The PHY_RST# logic also can be configured by the DSP accessed register. DSP SPI : DSP_SSPCS1 I DSP SPI Chip Select 1 : This signal is connected to the TMS320C6678 DSP SPISCS1 pin. The falling edge of the SSPCS1 from the DSP will initiate a transfer. If SSPCS1 is high, no data transfer can take place. DSP_SSPCK I DSP SPI Serial Clock : This signal is connected to the TMS320C6678 DSP SPICLK pin. The FPGA SPI bus clocks data in on the falling edge of SSPCK. Data transitions therefore occur on the rising edge of the clock. DSP_SSPMISO O DSP SPI Serial Data MISO : This signal is connected to the TMS320C6678 DSP SPIDIN pin. This signal is used for serial data transfers from the slave (FPGA) output to the master (DSP) input in the DSP_SSPCS1 asserted period. DSP_SSPMOSI I ...
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Pin Name IO Type Description DSP_GPIO[0 : 15] I/O DSP GPIO : In normal operation mode, these signals are not driven by the FPGA so that the DSP can use them as GPIO pins. During the EVM power‐on or during the RESETFULLz asserted period, the FPGA will output the BM_GPIO switch values to the DSP on these pins so the DSP can latch the boot mode configuration. DSP RESET & Interrupts Control : DSP_CORESEL[0:3] O DSP Core Selection Bit: The default value is 0000b and Register bits define the state of these pins. DSP_PACLKSEL O DSP PACLKSEL : This pin is used for the DSP PASS clock selection setting. The logic of this signal is derived from the BM_GPIO[13:11] state or configured by the FPGA registors. DSP_LRESETNMIENZ O Latch Enable for DSP Local Reset and NMI inputs :The default value is 1b and a register bit defines the state of this pin. DSP_NMIZ O DSP NMI. The default value is 1b and unlocked a register bit defines the state of this pin. DSP_LRESETZ O DSP Local Reset. The default value is 1b and a register bit defines the state of this pin. ...
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Pin Name IO Type Description DSP_TSIP1_FS[A:B]1 O DSP TSIP1_FS[A:B]1 : The single‐ended clock (DSP_TSIP1_FSA1 and DSP_TSIP1_FSB1) outputs are derived from the differential TDM Frame Synchronization (TDM_CLKC) input. DSP_TSIP0_CLK[A:B]0 O DSP TSIP0_CLK[A:B]0 : The single‐ended clock (DSP_TSIP0_CLKA0 and DSP_TSIP0_CLKB0) outputs are derived from the differential TDM clock (TDM_CLKA) input. DSP_TSIP1_CLK[A:B]1 O DSP TSIP1_CLK[A:B]1 : The single‐ended clock (DSP_TSIP1_CLKA1 and DSP_TSIP1_CLKB1) outputs are derived from the differential TDM clock (TDM_CLKA) input. TDM_CLKA[p/n] I, Diff TDM_CLKA Different Clock Input Pair The reference clock referring to the TSIP0/1 CLKs of the DSP. TDM_CLKB[p/n] I, Diff TCLKB Differential Clock Input Pair (RFU) (RFU) Telecom reference clock B from the AMC Backplane (FRU). On Rev3.0 and later version EVMs, the TCLKB could be used as an external clock reference for the common timing of the HyperLInk SERDES. TDM_CLKC[p/n] ...
Pin Name IO Type Description NAND_WP# O NAND Flash Write Protect : This signal is used to control the NAND flash write‐protect function. NOR_WP# O NOR Flash Write Protect : This signal is used to control the NOR flash write‐protect function. EEPROM_WP O EEPROM Write Protect : This signal is used to control the EEPROM write‐protect function. PCIESSEN I PCIE Subsystem Enable: This is used for the PCIESSEN switch input. USER_DEFINE I User Defined Switch: This is reserved for the user defined switch input. ICS557_SEL O PCIE clock Multiplexor input selection: This pin is controlled by a register to select PCIE reference clock from the CDCE62005 or the AMC edge connector. The default is from the CDCE62005. Also, when PCIe boot mode is selected, SW5.3 controls the default level for the register and this clock select. ICS557_PD# O PCIE clock Multiplexor Power Down: This pin is used to control the ICS557‐08 PD# pin, it’s de‐asserted after VCC1V5 valid. ICS557_OE O ...
5.3.4 Boot Configuration Forced in I2C Boot 5.3.1 Power‐On Sequence The following section provides details of the FPGA Power‐On sequence of operation. 1. After the EVM 3.3V auxiliary voltage (VCC3V3_AUX_PGOOD) is valid and stable, and the FPGA design code is loaded, the FPGA is ready for the Power‐On sequence of operation. 2. The FPGA starts to execute the Power‐On sequence. Wait for 10 ms, the FPGA enable the 2.5V power. 3. Once the 2.5V voltages (VCC5_PGOOD and VCC2V5_PGOOD) is valid, wait for 5 ms, the FPGA asserts the UCD9222_ENA1 and UCD9222_ENA2 to enable the CVDD and VCC1V0 DSP core power. 4. After both the UCD9222_PG1, UCD9222_PG2 and PGUCD9222 are all valid, wait for 5 ms, the FPGA enables the 1.8V power. 5. After the 1.8V voltage is valid (VCC1V8_PGOOD asserted), wait for 5 ms and then: • Unlock the 1.8V outputs on the FPGA, • De‐asserted CDCE62005#2_PD# pin, after driving CDCE62005_PD# to high for 1mS, the FPGA starts to initialize the CDCE62005 clock generator #2. ...
Following section provides details of FPGA power off sequence of operation. 1. Once the system powers on, any power failure events (any one of power good signals de‐asserted) will trigger the FPGA to proceed to the power off sequence. 2. Once any de‐asserted Power Good signals have been detected by the FPGA, the FPGA will assert the DSP_PORz and DSP_RESETFULLz to DSP immediately. 3. Wait for 5 ms, the FPGA will disable all the system power rails by the enable pins and two CDCE62005 clock generators by the power down pins, assert all the other DSP resets to DSP, lock the +1.8V output pins from the FPGA to the DSP. 4. FPGA remains in the power failure state until main 12V power is removed and restored. ...
Figure 5.2: Reset‐Full Switch/Trigger Boot Configuration Timing 5.3.4 Boot Configuration Forced in I2C Boot Note: This workaround is only needed with PG1.0 samples of the TMS320C6678 DSP. For reliable PLL operation at boot‐up, the FPGA will force the DSP to boot from the I2C by providing the boot configuration value as 0x0405 on the boot mode pins [12:0]. After the code in the I2C SEEPROM executes to initialize the PLLs, it will read the true values on the DIP switches from the registers in the FPGA and then boot as if the normal boot sequence had occurred The exception for the forced I2C boot is the emulation boot. The FPGA will not perform the I2C boot configuration override when the DIP switches have the following configuration: BOOTMODE[2:0] (GPIO[3:1]) = [000] and BOOTMODE[5:4] (GPIO[6:5]) = [00]. Therefore, the additional logic of the FPGA will allow the emulation boot to latch directly from the DIP switches. 5.4 Reset definition 5.4.1 Reset Behavior Power‐On : The Power‐On behavior includes initiating and sequencing the power sources, clock sources and then DSP startup. Please refer to the section 5.5.1 for detailed sequence and operations. Full Reset : The RESETFULLz is asserted low to the DSP. This causes RESETSTAT# to go low which triggers the boot configuration to be driven from the FPGA. Reset to the Marvell PHY is also asserted. POR# and RESET# to the DSP remain high. The 69 ...
power supplies and clocks operate without interruption. Please refer to the section 5.5.3 for detailed timing diagrams. Warm Reset : The RESETz is asserted low to the DSP. The PORz and RESETFULLz to the DSP remain high. The power supplies and clocks operate without interruption. 5.4.2 Reset Switches and Triggers FULL_RESET (RST_FULL1) – a logic low state with a low to high transition will trigger a Full Reset behavior event. When the push button switch RST_FULL1 is pressed, FPGA on EVM will assert DSP’s RESETFULL# input to issue a total reset of the DSP, everything on the DSP will be reset to its default state in response to this event, boot configurations will be latched and the ROM boot process will be initiated. ...
self‐refresh mode before invoking the soft reset. • PCIe MMRs: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not reset. COLD_RESET (RST_COLD1) – not used in current implementation. MMC_POR_IN_AMC# ‐ a logic low state with a low to high transition will trigger a Full Reset behavior event. MMC_WR_AMC# ‐ a logic low state with a low to high transition will trigger a warm reset behavior event. TRGRSTz ‐ a logic low state with a low to high transition on the Target Reset signal from emulation header will trigger a warm reset behavior event. FPGA_JTAG_RST# ‐ not used in current implementation. 5.5 SPI protocol This section describes the FPGA SPI bus protocol design specification for interfacing with TMS320C6678 DSP and CDCE62005 clock generators. It contains: 5.5.1 FPGA‐DSP SPI Protocol 5.5.2 FPGA‐CEDC62005(Clock Generator) SPI Protocol 5.5.3 The FPGA‐ programming CDCE62005 from the DSP 5.5.4 CDCE62005 programming sequences on the FPGA 5.5.5 CDCE62005 default value on the EVM 5.5.1 FPGA‐DSP SPI Protocol The FPGA supports the simple write and read commands for the TMS320C6678 DSP to access the FPGA configuration registers through the SPI interface. The FPGA SPI bus clocks data in on the falling edge of DSP SPI Clock. Data transitions therefore occur on the rising edge of the clock. ...
Figure 5.3: The SPI access form the TMS320C6678 to the FPGA (WRITE / high level) Figure 5.4: The SPI access form the TMS320C6678 to the FPGA (WRITE) The below figures illustrate a DSP to FPGA SPI read operation. Figure 5.5: The SPI access form the TMS320C6678 to the FPGA (READ / high level) 72 ...
Figure 5.6: The SPI access form the TMS320C6678 to the FPGA (READ) 5.5.2 FPGA‐ CDCE62005(Clock Generator) SPI Protocol The FPGA‐Clock Generator SPI interface protocol is compatible to CDCE62005 SPI. The FPGA SPI bus clocks data in on the rising edge of DSP SPI Clock. Data transitions therefore occur on the falling edge of the clock. The figure below illustrates a FPGA to CDCD62005 SPI write operation. Figure 5.7: The SPI access form the FPGA to the CDCE62005 (WRITE) The figure below illustrates a FPGA to CDCD62005 SPI read operation. Figure 5.8: The SPI access form the FPGA to the CDCE62005 (READ) 73 ...
5.5.3 The FPGA‐ programming CDCE62005 from the DSP This section describes how to configure the CDCE62005 clock generators by the SPI interface from the DSP to the FPGA. How to configure CDCE62005 for the clock outputs: Programming sequence of CDCE62005 via the FPGA by the DSP is setting the desire values to the relevant offsets on the FPGA for the settings on the Register[0:7] of CDCE62005 and issues a “start command (send)” by offset 0x10h on the FPGA to conduct programming sequences to CDCE62005. There are eight banks (Register[0:7]) inside the FPGA mapping to eight registers of CDCE62005 by the same offsets for the CLK#2 and CLK3. Configuring the Clock Generator#2 (CDCE62005) by the DSP is described as below for example. The CLK#2 offset on the FPGA are 0x17h (MSB) to 0x14h (LSB), they are including 28‐bit data field and 4‐bit addr. Field as the same of CDCE62005, user can refer to CDCE62005 specification on TI website for the configuration details. Offset Register definitions Type Default 0x10h CLK‐GEN 2 Control Register R/W 0x00h 0x11h CLK‐GEN 2 Interface Clock Setting 0x03h 0x14h CLK‐GEN 2 Command Byte 0 0x00h 0x15h CLK‐GEN 2 Command Byte 1 0x00h 0x16h CLK‐GEN 2 Command Byte 2 R/W 0x00h 0x17h ...
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a. Check the bits 0 of ‘Busy Status’ on offset 0x10h to make sure the last progress have been finished. b. Set address 0x00h to the offset 0x14h, the last 4‐bit were set for the Register 0; c. Set data 0xEBh, 0x86h, 0x03h and 0x00h to the offset 0x17h, 0x16h, 0x15h and 0x14h respectively for the new configurations of the clock output0; d. Set address 0x04h to the offset 0x14h, the last 4‐bit were set for the Register 4; e. Set data 0x69h, 0x86h, 0x03h and 0x14h to the offset 0x17h, 0x16h, 0x15h and 0x14h respectively for the new configurations of the clock output4; f. The Register 0 and Register 4 on the FPGA for CLK‐GEN#2 are updated by the DSP. g. Please note that the default values in the Register[0:7] are the same of values initialized during power‐on phase. 2. The DSP sets offset 0x10h bit 0 on the FPGA to upload the configurations to CDCE62005 (CLK‐GEN#2). a. The offset 0x10h bit 0 on the FPGA is “initiate/start the data transfer” bit. The FPGA will program the CDCE62005 by the values of the Register[0:7] inside the FPGA via the SPI interface if this bit is set (‘1’). b. If any of reset events needed after re‐programming the CLK GEN, please set the FPGA offset 0x10h register bits 2, 3, or(and) 4 for DSP_PORz, DSP_RESETFULLz or RESETz. The FPGA will issue the reset events based on the offset 0x10h bit[2:4] after finished CDCE62005 programming. ...
through the FPGA offset 1Bh~18h registers once the SPI protocol is completed. The detail steps are : a. The DSP sets value of 0x8Eh to the FPGA offset 0x14h register (0x8h ‐> Register8; 0xEh ‐> reading); b. The DSP clears the FPGA offset 0x15h, 0x16h, and 0x17h registers by 0x00h; c. The DSP sets 0x01h to the FPGA offset 10h register (issue the SPI protocol), The bit 0 of the offset 0x10h register means “initiate/start the data transfer”. The data field on the offset 0x17h‐0x14h registers will be sent to the 2nd Clock Generator CDCE62005 via the SPI interface to indicate the reading register number if this bit is set to ‘1’.); d. DSP checks the FPGA offset 0x10h register bit 1; The FPGA offset 0x10h register bit1 means “Busy status” and it is used to indicate the CDCE62005 SPI bus status. The SPI bus is busy and a SPI command is processing while this bit is read as ‘1’. ...
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Attribute : Read Only Bit Description Read/Write 7‐0 FPGA Device ID (High Byte) This field combined with the offset 00h field identifies the RO particular device. This identifier is allocated by the FPGA design team. Register Address : SPI Base + 02h Register Name : FPGA Revision ID (Low Byte) Register Default Value: ** Attribute : Read Only Bit Description Read/Write 7‐0 FPGA Revision ID (Low Byte) This offset 03h register combined with this register specifies the RO FPGA device specific revision identifier. The value may be changed in the future FPGA FW update release.
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Bit Description Read/Write 1 : BM GPIO 03 state is high 4 BM GPIO 04 : This bit reflects the state of the BM general purpose input signal GPIO 04 and writes will have no effect. RO 0 : BM GPIO 04 state is low 1 : BM GPIO 04 state is high 5 BM GPIO 05 : This bit reflects the state of the BM general purpose input signal GPIO 05 and writes will have no effect. RO 0 : BM GPIO 05 state is low 1 : BM GPIO 05 state is high 6 BM GPIO 06 : This bit reflects the state of the BM general purpose input signal GPIO 06 and writes will have no effect. RO 0 : BM GPIO 06 state is low 1 : BM GPIO 06 state is high 7 BM GPIO 07 : This bit reflects the state of the BM general purpose input signal GPIO 07 and writes will have no effect. RO 0 : BM GPIO 07 state is low 1 : BM GPIO 07 state is high Register Address : SPI Base + 05h Register Name : BM GPI (15‐08 High Byte) Status Register Default Value: ...
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Bit Description Read/Write 1 : BM GPIO 13 state is high 6 BM GPIO 14 : This bit reflects the state of the BM general purpose input signal GPIO 14 and writes will have no effect. RO 0 : BM GPIO 14 state is low 1 : BM GPIO 14 state is high 7 BM GPIO 15 : This bit reflects the state of the BM general purpose input signal GPIO 15 and writes will have no effect. RO 0 : BM GPIO 15 state is low 1 : BM GPIO 15 state is high Register Address : SPI Base + 06h Register Name : DSP GPI (07‐00 Low Byte) Register Default Value: ‐‐‐‐ Attribute : Read Only Bit Description Read/Write 0 DSP GPIO 00 : This bit reflects the state of the DSP general purpose input signal GPIO 00 and writes will have no effect. RO 0 : DSP GPIO 00 state is low 1 : DSP GPIO 00 state is high 1 ...
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1 : DSP GPIO 07 state is high Register Address : SPI Base + 07h Register Name : DSP GPI (15‐08 High Byte) Status Register Default Value: 00h Attribute : Read Only Bit Description Read/Write 0 DSP GPIO 08 : This bit reflects the state of the DSP general purpose input signal GPIO 08 and writes will have no effect. RO 0 : DSP GPIO 08 state is low 1 : DSP GPIO 08 state is high 1 DSP GPIO 09 : This bit reflects the state of the DSP general purpose input signal GPIO 09 and writes will have no effect. RO 0 : DSP GPIO 09 state is low 1 : DSP GPIO 09 state is high 2 DSP GPIO 10 : This bit reflects the state of the DSP general purpose input signal GPIO 10 and writes will have no effect. RO 0 : DSP GPIO 10 state is low 1 : DSP GPIO 10 state is high 3 DSP GPIO 11 : This bit reflects the state of the DSP general purpose input signal GPIO 11 and writes will have no effect. RO ...
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Register Address : SPI Base + 08h Register Name : Debug LED Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 0 DEBUG_LED 1 : This bit can be updated by the DSP software to drive a high or low value on the debug LED 1 pin. R/W 0 : DEBUG_LED 1 drives low and set the LED 1 to ON. 1 : DEBUG_LED 1 drives high and set the LED 1 to OFF. 1 DEBUG_LED 2 : This bit can be updated by the DSP software to drive a high or low value on the debug LED 2 pin. R/W 0 : DEBUG_LED 2 drives low and set the LED 2 to ON. 1 : DEBUG_LED 2 drives high and set the LED 2 to OFF. 2 DEBUG_LED 3 : This bit can be updated by the DSP software to drive a high or low value on the debug LED 3 pin R/W 0 : DEBUG_LED 3 drives low and set the LED 3 to ON. 1 : DEBUG_LED 3 drives high and set the LED 3 to OFF. 3 DEBUG_LED 4 : This bit can be updated by the DSP software to drive a high or low value on the debug LED 4 pin R/W 0 : DEBUG_LED 4 drives low and set the LED 4 to ON. ...
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current state. 3 MMC_WR_AMC# : This bit reflects the MMC_WR_AMC# state and it is used by the MMC to trigger a warm reset event. 0 : MMC_WR_AMC# state is low to trigger a warm reset event. RO 1 : MMC_WR_AMC# state is high and the FPGA stays in current state 4 MMC_BOOTCOMPLETE: This bit reflects the DSP_BOOTCOMPLETE state and the FPGA will drive the same logic value on the MMC_ BOOTCOMPLETE pin ( to MMC ). 0 : DSP_BOOTCOMPLETE state is low and the FPGA drives MMC_ RO BOOTCOMPLETE low to MMC 1 : DSP_BOOTCOMPLETE state is high and the FPGA drives MMC_ BOOTCOMPLETE high to MMC 7‐5 Reserved RO Register Address : SPI Base + 0Ah Register Name : PHY Control Register Default Value: 03h Attribute : Read/Write Bit Description Read/Write 0 ...
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Bit Description Read/Write 1 : WARM_RESET button state is high 2 COLD_RESET button status (RFU): This bit reflects the COLD _RESET button state. This button is not used in current implementation. RO 0 : COLD_RESET button state is low 1 : COLD_RESET button state is high 3 FPGA_JTAG_RST# 0 : FPGA_JTAG_RST# state is low RO 1 : FPGA_JTAG_RST# state is high 4 DSP_RESETSTAT# : This bit reflects the DSP_RESETSTAT# state. 0 : DSP_RESETSTAT# state is low RO 1 : DSP_RESETSTAT# state is high 5 TRGRSTZ : This bit reflects the TRGRSTZ state. 0 : TRGRSTZ state is low RO 1 : TRGRSTZ state is high 6 PCIESSEN : This bit reflects the PCIESSEN switch state. 0 : PCIESSEN state is low RO 1 : PCIESSEN state is high 7 User_Defined Switch : This bit reflects the User_Define Switch state. RO 0 : User_Defined Switch state is low 1 : User_Defined Switch state is high ...
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0 : PCA9306_EN drives low (Default) 1 : PCA9306_EN drives high 7 Reserved RO Register Address : SPI Base + 0Dh Register Name : Miscellaneous ‐ 2 Register Default Value: ‐‐‐‐ Attribute : Read Only Bit Description Read/Write 0 FPGA FW Update SPI Interface Enable Status : This bit reflects the FPGA FW Update SPI Interface Enable status. The FPGA FW Update SPI interface could be enabled/disabled through the offset 0Eh register. 0 : FPGA FW update SPI interface is disabled. RO 1 : FPGA FW update SPI interface is enabled. The DSP_GPIO[12] is mapped to FPGA_FW_SPI_CLK. The DSP_GPIO[13] is mapped to FPGA_FW_SPI_CS#. The DSP_GPIO[14] is mapped to FPGA_FW_SPI_MOSI. ...
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Register Address : SPI Base + 0Fh Register Name : Scratch Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 7‐0 Scratch Data R/W Register Address : SPI Base + 10h Register Name : CLK‐GEN 2 Control Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 0 Initiate a data transfer via the SPI bus to update the SPI command to CDCE62005 Clock Generator #2 R/W ...
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05 : CDCE62005 2 SPI Clock = 4 MHz ( = 48 /12 ) 06 : CDCE62005 2 SPI Clock = 3.42 MHz ( = 48 / 14) …… X : CDCE62005 2 SPI Clock = 48 MHz /((X+1)*2) if X != 0 Register Address : SPI Base + 12h ~ 13h Register Name : Reserved Register Address : SPI Base + 14h Register Name : CLK‐GEN 2 Command Byte 0 Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 7‐0 This register specifies the update SPI command byte 0 to the CDCE62005 Clock Generator #2 R/W 3‐0 : SPI command address field bit 3 to bit 0 7‐4 : SPI command data field bit 3 to bit 0 Register Address : SPI Base + 15h Register Name : CLK‐GEN 2 Command Byte 1 Register ...
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Register Address : SPI Base + 18h Register Name : CLK‐GEN 2 Read Data Byte 0 Register Default Value: 00h Attribute : Read Only Bit Description Read/Write 7‐0 This register reflects the read back data byte 0 from the CDCE62005 Clock Generator #2 for responding a host SPI Read Command. RO 7‐0 : The SPI read back data bit 7 to bit 0 for a SPI Read Command. Register Address : SPI Base + 19h Register Name : CLK‐GEN 2 Read Data Byte 1 Register Default Value: 00h Attribute : Read Only Bit Description Read/Write 7‐0 ...
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Register Address : SPI Base + 1Ch ~ 1Fh Register Name : Reserved Register Address : SPI Base + 20h Register Name : CLK‐GEN 3 Control Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 0 Initiate a data transfer via the SPI bus to update the SPI command to CDCE62005 Clock Generator #3 R/W 0 : Idle state 1 : Write 1 to perform the SPI command update process. 1 The BUSY status indication for the CDCE62005 Clock Generator #3 SPI bus 0 : The SPI bus for the CDCE62005 Clock Generator #3 is idle. RO 1 : The SPI bus for the CDCE62005 Clock Generator #3 is busy and a SPI command is processing. 2 DSP_PORZ signal will generate one active pulse after data transfer sequence is finished R/W ...
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Register Address : SPI Base + 22h ~ 23h Register Name : Reserved Register Address : SPI Base + 24h Register Name : CLK‐GEN 3 Command Byte 0 Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 7‐0 This register specifies the update SPI command byte 0 to the CDCE62005 Clock Generator #3 R/W 3‐0 : SPI command address field bit 3 to bit 0 7‐4 : SPI command data field bit 3 to bit 0 Register Address : SPI Base + 25h Register Name : CLK‐GEN 2 Command Byte 1 Register Default Value: 00h Attribute : ...
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Register Address : SPI Base + 28h Register Name : CLK‐GEN 3 Read Data Byte 0 Register Default Value: 00h Attribute : Read Only Bit Description Read/Write 7‐0 This register reflects the read back data byte 0 from the CDCE62005 Clock Generator #3 for responding to a host SPI Read Command. 3‐0: The SPI read back register address [3‐0] for a SPI Read RO Command 7‐4 : The SPI read back data bit 3 to bit 0 for a SPI Read Command. Register Address : SPI Base + 29h Register Name : CLK‐GEN 3 Read Data Byte 1 Register Default Value: 00h Attribute : Read Only Bit ...
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Register Address : SPI Base + 2Ch ~ 2Fh Register Name : Reserved Register Address : SPI Base + 30h ~ 3Fh(TBD) Register Name : PM Bus Control Register Default Value: 00h Attribute : Read/Write Bit Description Read/Write 7‐0 TBD R/W Register Address : SPI Base + 40h ~ 4Fh Register Name : Reserved Register Address : SPI Base + 50h Register Name : ICS 557 Clock Selection Control Register Default Value: 00h ...
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