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Section 17 Serial Communication Interface with FIFO (SCIF)
17.5
Interrupt Sources
Table 17.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt
source.
When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU.
The SERIRQ signal of the LPC interface transmits an interrupt request to the host.
Table 17.9 Interrupt Sources
Interrupt Name
Receive line status
Receive data ready
Character timeout
(when FIFO is enabled)
FTHR empty
Modem status
Table 17.10 shows the interrupt source, vector address, and interrupt priority.
Table 17.10 Interrupt Source, Vector Address, and Interrupt Priority
Interrupt
Origin of Interrupt Source
SCIF
17.6
Usage Note
17.6.1
Power-Down Mode When LCLK is Selected for SCLK
To switch to watch mode or software standby mode when LCLK divided by 18 has been selected
for SCLK, use the shutdown function of the LPC interface to stop LCLK.
Rev. 1.00 Apr. 28, 2008 Page 528 of 994
REJ09B0452-0100
Interrupt Source
Overrun error, parity error, framing error, break interrupt
Acceptance of receive data, FIFO trigger level
No data is input to or output from the receive FIFO for the 4-
character time period while one or more characters remain in
the receive FIFO.
FTHR empty
CTS, DSR, RI, DCD
Interrupt Name
SCIF (SCIF interrupt)
Vector
Vector
Number
Address
82
H'000148
Priority
High
Low
ICR
ICRC7
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