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(c) Write timing (SRAM, external ROM, external I/O)
Figure 1-5. Write Timing (SRAM, External ROM, External I/O)
BUSCLK (output)
A0-A25, CSZ0-CSZ7
(output)
RDZ, IORDZ (output)
WRZ0-WRZ3, WRSTBZ
(output)
D0-D31 (I/O)
WAITZ (input)
BCYSTZ (output)
Note
In the case of CSZ0-CSZ7
Remarks 1. Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the number
of idle states inserted by the BCC register is 1, and the number of waits inserted by the ASC
register is 1.
2.
Broken lines indicate high impedance.
22
CHAPTER 1 PRODUCT SPECIFCATIONS
TASW
T1
< t
>
DKA
< t
>
DKRDH
< t
>
DKWRH
< t
>
DKOD
< t
HKW
< t
>
SKW
< t
>
< t
DKBSL
User's Manual A19069EJ2V0UM
TW
T2
< t
>
< t
DKWRL
>
< t
>
HKW
< t
>
SKW
>
DKBSH
TI
< t
>
DKA
Note
< t
>
DKRDL
< t
>
DKWRL
>
DKWRH
< t
>
HKOD
< t
>
D KBSL
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