Figure 8.1 External Port & Host Interface - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
Any host microprocessor with a standard memory interface can easily
connect to the ADSP-2106x bus through buffers. By providing an
address, a data bus, and memory control signals—i.e. read, write and
chip select—a host may access any device on the ADSP-2106x bus as if
it were a memory. The host data bus width may be either 16 or 32 bits,
and the host-driven address may be either 8 or 32 bits. Any one of
ADSP-2106xs on the bus can be addressed, either with their chip select
CS
( ) signal or with a memory-mapped address. All of the internal
registers and resources of the ADSP-2106x's I/O processor, such as the
DMA control registers, are available to the host. A host bus
acknowledge signal, REDY, is provided to indicate the completion of
each transfer.
Core Internal Memory
Processor
PM Address Addr
DM Address Addr
Addr
IOA
PM Data
DM Data
I/O Address
17
Bus (IOA)
Figure 8.1 External Port & Host Interface
8 – 2
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Data Data Data
PMD DMD IOD
I/O Data
48
Bus (IOD)
External Port
FIFO Buffers
(6-deep)
EPB0 EPB2
EPB1 EPB3
Other IOP Registers
Direct Write FIFO
(6-deep)
I/O Processor
External Port
PMA
DMA
PMD
DMD
Slave Write FIFO
EPD
(Async writes - 4 deep)
(Sync writes - 2 deep)
EPA
Buffer
Ext. Port Ext. Port
48 32
Data Bus Address
(EPD) Bus (EPA)
32
ADDR
31-0
48
DATA
47-0
Host-driven accesses go
to the I/O Processor