Dma Throughput - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
DMAGx
If the external device is writing data to the latch, the signal is
used as the output enable signal for the latch. If the external device is
DMAGx
reading from the latch, is used to clock the data on its rising
DMARx
edge. Figure 6.12 shows the timing relationships between ,
DMAGx
, and the data transfer. Refer to the ADSP-2106x Data Sheet for
exact specifications.
6.5

DMA THROUGHPUT

This section discusses overall DMA throughput when several DMA
channels are trying to access internal or external memory at the same
time.
Internal Memory DMA
The DMA channels arbitrate for access to the ADSP-2106x's internal
memory. The DMA controller determines, on a cycle-by-cycle basis,
which channel is allowed access to the internal I/O bus and
consequently which channel will read or write to internal memory.
(The priority of the DMA channels is shown in Table 6.13 in the "DMA
Channel Prioritization" section of this chapter.)
Each DMA transfer takes one clock cycle even when different DMA
channels are being allowed access on sequential cycles; i.e. there is no
overall throughput loss in switching between channels. Thus, four link
port DMA channels, each transferring one byte per cycle, would have
the same I/O transfer rate as one external port DMA channel
transferring data to internal memory on every cycle. Any combination
of link ports, serial ports, and external port transfers has the same
maximum transfer rate.
External Memory DMA
When the DMA transfer is between ADSP-2106x internal memory and
external memory, the external memory may have one or more wait
states. External memory wait states, however, do not reduce the
overall internal DMA transfer rate if other channels have data
available to transfer. In other words, the ADSP-2106x's internal I/O
data bus will not be held up by an incomplete external transfer.
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