Packet Structure And Coding; Programming After Initial Power-Up - Analog Devices ADF7021-V Manual

RFIN
RFIN
Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller
The calibration results are valid over changes in the ADF7021-V
supply voltage. However, there is some variation with temperature.
A typical plot of variation in image rejection over temperature
after initial calibrations at −40°C, +25°C, and +85°C is shown in
Figure 52. The internal temperature sensor on the ADF7021-V
can be used to determine whether a new IR calibration is required.
60
50
40
CAL AT +85°C
30
V = 3.0V
DD
IFBW = 25kHz
20
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
10
DATA = PRBS9
f
= 4kHz
DEV
LEVEL= –100dBm
0
–60 –40 –20 0
TEMPERATURE (°C)
Figure 52. Image Rejection vs. Temperature After Initial Calibrations
at −40°C, +25°C, and +85°C
LNA
MUX
INTERNAL
SIGNAL
SOURCE
CAL AT +25°C
CAL AT –40°C
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
DATA = PRBS11
f
= 4kHz
DEV
20 40 60 80 100
ADF7021-V
POLYPHASE
IF FILTER
PHASE ADJUST
I Q
FROM LO
SERIAL
INTERFACE
4
PHASE ADJUST
REGISTER 5
RSSI READBACK
4
GAIN ADJUST
REGISTER 5
MICROCONTROLLER
I/Q GAIN/PHASE ADJUST AND
RSSI MEASUREMENT
ALGORITHM

PACKET STRUCTURE AND CODING

The suggested packet structure to use with the ADF7021-V is
shown in Figure 53.
PREAMBLE
Figure 53. Typical Format of a Transmit Protocol
See the Receiver Setup section for information about the required
preamble structure and length for the various modulation schemes.

PROGRAMMING AFTER INITIAL POWER-UP

Table 23 lists the minimum number of writes needed to set up
the ADF7021-V in either Tx or Rx mode after CE is brought
high for a minimum of 100 μs before programming any register.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection
or enabling AFC. When going from Tx to Rx or vice versa, the
user needs to toggle the Tx/Rx bit and write only to Register 0
to alter the LO by 100 kHz.
Table 23. Minimum Register Writes Required for Tx/Rx Setup
Mode
Tx
Rx
Tx to Rx and Rx to Tx
Rev. 0 | Page 39 of 60
RSSI/
LOG AMP
7-BIT
ADC
SYNC ID
DATA FIELD
WORD FIELD
Required Register Writes
Reg 1, Reg 3, Reg 0, Reg 2
Reg 1, Reg 3, Reg 5, Reg 0, Reg 4
Reg 0
ADF7021-V
CRC