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Division Exceptions
B.1
DIVISION FUNDAMENTALS
The ADSP-2100 family processors' instruction set contains two
instructions for implementing a non-restoring divide algorithm. These
instructions take as their operands twos-complement or unsigned
numbers, and in sixteen cycles produce a truncated quotient of sixteen
bits. For most numbers and applications, these primitives produce the
correct results. However, there are certain situations where results
produced will be off by one LSB. This appendix documents these
situations, and presents alternatives for producing the correct results.
Computing a 16-bit fixed point quotient from two numbers is
accomplished by 16 executions of the DIVQ instruction for unsigned
numbers. Signed division uses the DIVS instruction first, followed by
fifteen DIVQs. Regardless of which division you perform, both input
operands must be of the same type (signed or unsigned) and produce a
result of the same type.
These two instructions are used to implement a conditional add/subtract,
non-restoring division algorithm. As its name implies, the algorithm
functions by adding or subtracting the divisor to/from the dividend. The
decision as to which operation is perform is based on the previously
generated quotient bit. Each add/subtract operation produces a new
partial remainder, which will be used in the next step.
The phrase non-restoring refers to the fact that the final remainder is not
correct. With a restoring algorithm, it is possible, at any step, to take the
partial quotient, multiply it by the divisor, and add the partial remainder
to recreate the dividend. With this non-restoring algorithm, it is necessary
to add two times the divisor to the partial remainder if the previously
determined quotient bit is zero. It is easier to compute the remainder
using the multiplier than in the ALU.
B.1.1
Signed Division
Signed division is accomplished by first storing the 16-bit divisor in an X
register (AX0, AX1, AR, MR2, MR1, MR0, SR1, or SR0). The 32-bit
dividend must be stored in two separate 16-bit registers. The lower 16-bits
must be stored in AY0, while the upper 16-bits can be in either AY1, or
AF.
B
B – 1
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