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System window watchdog (WWDG)
45.5.2
WWDG configuration register (WWDG_CFR)
Address offset: 0x004
Reset value: 0x0000 007F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wakeup interrupt
Bits 8:7 WDGTB[1:0]: Timer base
Bits 6:0 W[6:0]: 7-bit window value
45.5.3
WWDG status register (WWDG_SR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
45.5.4
WWDG register map
The following table gives the WWDG register map and reset values.
1544/2301
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
EWI
rs
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK div 4096) div 1
01: CK Counter Clock (PCLK div 4096) div 2
10: CK Counter Clock (PCLK div 4096) div 4
11: CK Counter Clock (PCLK div 4096) div 8
These bits contain the window value to be compared with the down-counter.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not
enabled.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
WDGTB[1:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
5
4
3
2
W[6:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
Res.
EWIF
rc_w0
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