ST STM32L4+ Series Reference Manual page 1543

RM0432
more details refer to
and I2C.
45.4 WWDG interrupts
The early wakeup interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the actual reset is generated. The EWI interrupt is enabled by
setting the EWI bit in the WWDG_CFR register. When the down-counter reaches the value
0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)
can be used to trigger specific actions (such as communications or data logging), before
resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case, the corresponding interrupt service routine (ISR) has to reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset is eventually generated.
45.5 WWDG registers
Refer to
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).
45.5.1 WWDG control register (WWDG_CR)
Address offset: 0x000
Reset value: 0x0000 007F
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
Section 48.16.2: Debug support for timers, RTC, watchdog, bxCAN
Section 1.2 on page 84
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter, decremented every
[1:0]
WDGTB
(4096 x 2 ) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).
System window watchdog (WWDG)
for a list of abbreviations used in register descriptions.
24 23 22
Res. Res. Res. Res.
8 7 6
Res. WDGA
rs rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
T[6:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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