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UM-WI-006
DA16200 H/W Design Guide
2.6
Serial Flash
2.6.1
Serial Flash Interface
VDD_FDIO
R5
DNI
F_CSN
F_IO1
F_IO2
The QSPI master supports 4-line SPI communication with commercial flash memory devices and
uses a Motorola SPI-compatible interface among SPI communication modes. The highest
communication speed is the same as the AMBA bus clock, and the speed is adjustable in integer
multiples. The designed QSPI supports 4-/2-/1-line types depending on the purpose. These types
should be combined. Especially when 1-line communication mode is used, it can be used as the SPI
master.
Table 7
shows the connections between DA16200 and serial flash.
Table 7: Connections Between DA16200 and Serial Flash
DA16200
Pin name
QFN
F_IO0
14
F_IO1
15
F_IO2
16
F_IO3
17
F_CSN
18
F_CLK
19
2.6.2
Serial Flash Selection Guide
SFDP (Serial Flash Discoverable Parameters) is a standard table for the main parameters of serial
flash defined by JEDEC. This is information about the characteristics (access timing, supported
commands, delay parameter) of each serial flash manufactured by various vendors, which should be
optimized for each serial flash.
NOTE
The FreeRTOS SDK supports flash sizes greater than 4MB.
Currently the DA16200 SDK supports SFDP tables for serial flashes listed in
User Manual
CFR0012
R6
10K
1
2
Serial Flash
3
4
Figure 13: Serial Flash Application Schematic
Serial Flash
fcCSP
Pin name
K8
DI / SI / IO0
L7
DO / SO / IO1
J7
WP / IO3
K6
HOLD / RESET
J5
CSN / CSB
K4
CLK / SCK
Revision 1.5
20 of 44
R7
DNI
8
7
6
5
Note
Pin #
5
2
3
7
1
10 kΩ pull-up resistor
6
Table 8
© 2022 Renesas Electronics
NDA Confidential
F_IO3
F_CLK
F_IO0
below.
11-Apr-2022
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