Block Diagram - Texas Instruments CC11 1-Q1 Series Manual

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3.2

Block Diagram

A simplified block diagram of CC11x1-Q1 is shown in
intermediate frequency (IF) receiver. The received radio frequency (RF) signal is amplified by the
low-noise amplifier (LNA) and down-converted in a quadrature (I and Q) to the IF. At IF, the I/Q signals
are digitized by the analog-to-digital converters (ADCs). Automatic gain control (AGC), fine channel
filtering, and demodulation bit/packet synchronization is performed digitally.
The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency
synthesizer includes a completely on-chip LC voltage-controlled oscillator (VCO) and a 90° phase shifter
for generating the I and Q signals, and it is also used for the down-conversion mixers in receive mode. A
crystal must be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference
frequency for the synthesizer as well as the clocks for the ADC and the digital part.
A 4-wire SPI serial interface is used for the register configuration and data buffer access. The digital base
band modem includes support for channel configuration, packet handling, Forward Error Correction and
data buffering.
In the CC1131-Q1 devices, the TX path is not available. In the CC1151-Q1 devices, the RX path is not
available.
RF_P
RF_N
RC OSC
CC11x1-Q1 features a low intermediate frequency (IF) receiver. The received RF signal is amplified by the
low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the IF. At IF, the I/Q signals are
digitized by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet
synchronization are performed digitally.
The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency
synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO
signals to the down-conversion mixers in receive mode.
A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference
frequency for the synthesizer, as well as clocks for the ADC and the digital part.
A 4-wire SPI serial interface is used for configuration and data buffer access.
The digital baseband includes support for channel configuration, packet handling, and data buffering.
Copyright © 2009–2010, Texas Instruments Incorporated
Radio Control
ADC
LNA
ADC
Frequency
0
Synthesizer
90
PA
BIAS XOSC
Figure 3-1. Simplified Block Diagram
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SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
Figure 3-1. The CC11x1-Q1 devices feature a low
CC11x1-Q1
SCLK
SO (GDO1)
SI
CS
GDO0 (ATEST)
GDO2
Detailed Description 19