Texas Instruments C2000 Technical Training Manual
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Texas Instruments C2000 Technical Training Manual

Digital power supply workshop
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C2000 Digital Power Supply
Workshop
Texas Instruments
Technical Training
D SP
TEXAS INSTRUMENTS
Copyright © 2008 Texas Instruments. All rights reserved.
TECHNOLOGY

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Summary of Contents for Texas Instruments C2000

  • Page 1 C2000 Digital Power Supply Workshop Texas Instruments Technical Training D SP TEXAS INSTRUMENTS Copyright © 2008 Texas Instruments. All rights reserved. TECHNOLOGY...
  • Page 2 Introduction to Digital Power Supply Design What is a Digital Power Supply? Why use Digital Control Techniques? Peripherals used for Digital Power Supply Design Development Tools and Software...
  • Page 3 What is Digital Power? Generic Power System Block Diagram Controller Switches Network (Compensator) (FETs) The controller block is what differentiates between a digital power system and a conventional analog power system...
  • Page 4 Why Digital Control Techniques? Controller Power Elec. Analog Sensor(s) Digital ?? Analog Controller Digital Controller High bandwidth Insensitive to environment (temp, drift,…) High reliability High resolution S/w programmable / flexible solution Easy to understand / use Precise / predictable behavior Historically lower cost Advanced control possible (non-linear, multi-variable) Can perform multiple loops and “other”...
  • Page 5 Benefits of Digital Control Filter DC/DC Output Bridge Traditional Analog Power Supply Inrush/ Inrush/ DC/DC DC/DC Current/Load Current/Load Hot-plug Hot-plug PFC Control PFC Control Converter Sharing Converter Sharing Control Control Control Control Control Control Multiple chips for control Multi-mode Multi-mode Interface Interface Power control...
  • Page 6 Analog Control System “Analog Computation” Differential equations       Differential equations   ,…order Need to find: Laplace Transform...
  • Page 7 Digital Control System Difference equation ⋅ − ⋅ − ⋅ − ⋅ − ⋅ where Κ − Need to find: Differential equations ,…order Laplace Transform Z Transform...
  • Page 8 Time Sampled Systems...
  • Page 9 Processor Bandwidth Sample Freq (=PWM) Sample Period (kHz) (ns) 10000 3333 2000 1429 1000 1000 1500 2000...
  • Page 10 Time Division Multiplexing (TDM) y(n) SAMPLE x(n) Processor 1 Control Code (C1) Control Code Control Processor 2 Control Code (C2) Control Code Control Processor 3 Control Code (C3) Control Code Control Single CPU...
  • Page 11 Digitally Controlled Power Supply (PWM) “Plant” 0110101100 1011011101 0010100111 “High fidelity” Translation boundary...
  • Page 12 System Mapping...
  • Page 13 TMS320F280x High Performance DSP (C28x Core) Code security 100MIPS performance 64Kw Flash 18Kw Single cycle 32 x32-bit MAC (or dual 16 x16 MAC) Boot + 1Kw OTP ePWM Very Fast Interrupt Response Single cycle read-modified-write eCAP Memory Sub-System Memory Bus eQEP Fast program execution out of both RAM and Flash memory...
  • Page 14 Efficient 32-bit Processor Capability C28x DSP Core Interrupt Management Single-cycle 32-bit multiplier makes computationally intensive control C28x 32-bit DSP algorithms more efficient 32x32 bit R M W Multiplier Atomic Three 32-bit timers support multiple control loops / time bases 32-bit Timers (3) Single cycle read-modified-write in any 32-bit...
  • Page 15 ePWM “DAC” Capability ePWM Control Peripherals Event ePWM EPWMxA Trip Trig. Time-Base Zone EPWMxB & Int. Number of channels scalable and resources allocated per Dead Counter Band Chop channel Compare Two independent PWM outputs per module Dedicated time-base timer PWM effective resolution (CPU=100MHz) Two independent compare registers HR-PWM...
  • Page 16 12-bit ADC Capability Control Peripherals SYSCLK Prescaler Fast & Flexible Analog 8 ADC 12-bit 16-Channel ADC Inputs Result 12-bit Registers 6.25 MSPS throughput Module 16 words 8 ADC Analog Inputs Dual sample/hold enable simultaneous sampling or sequencing sampling modes Start of Auto Sequencer Conversion Analog input: 0V to 3V...
  • Page 17 Code Composer Studio Menus or Icons Help Window Project Manager: Source & object files File dependencies Compiler, Assembler & Linker build options Full C/C++ & Assembly Debugging: C & ASM Source Mixed mode Disassembly (patch) Set Break Points Set Probe Points Editor: Structure Expansion Watch Window...
  • Page 18 Software Library Approach DPS software libraries available at: www.ti.com/dpslib...
  • Page 19 Modular Software Architecture “Signal Net” based module connectivity Initialization time Run time - ISR // pointer & Net declarations ; Execute the code Int *In1A, *In1B, *Out1, *In2A,... Int Net1, Net2, Net3, Net4,... // “connect” the modules In1A=&Net1; In1B=&Net2; In2A=&Net3; In3A=&Net4; // inputs Out4=&Net8;...
  • Page 20 Peripheral Drivers CPU dependency only: • Math / algorithms Depends on: • Per-Unit math (0-100%) • PWM frequency • Independent of Hardware • System clock frequency // pointer & Net declarations int *CNTL_Ref1, *CNTL_Fdbk1, *CNTL_Out1; int *BUCK_In1, *ADC_Rslt1; int Vref, Duty, Vout; Depends on: // “connect”...
  • Page 21 Dual Buck Example...
  • Page 22 Software Block Execution...
  • Page 23 Lab1: Exploring the Development Environment Navigate CCS features Understand DPS library structure Generate and visualize PWM waveforms TI PowerTrain Active Volt PTD08A010W Phase Links 10A module Load Meter LEDs Current meas. Temp meas Over Current Prot. Over Current Flag No Heat-sink needed controlCard 2808...
  • Page 24 Simple Open-Loop Diagram...
  • Page 25 Scaleable PWM Peripherals Each peripheral module has the same structure Resources allocated on a per channel basis Each channel (module) supports 2 independent PWM outputs (A&B) # Channels easily scaleable – software reuse Time-base synch feature for all channels 6 modules (12 PWM outputs) on F2808 Key features: Phase &...
  • Page 26 ePWM Module Block Diagram...
  • Page 27 Module Sync and Phase Control TBCTR FFFFh Master Module TBPRD 0000 CTR=Zero (SycnOut) time TBCTR FFFFh Phase = 120 Slave Module TBPRD TBPHS 0000 SyncIn time...
  • Page 28 Action Qualifier Module (AQM) Key Features Multi event driven waveform generator Events drive outputs A and B independently. Full control on waveform polarity Full transparency on waveform construction S/W forcing events supported All events can generate interrupts & ADC SOC TBCTR Period CMPB...
  • Page 29 Simple Waveform Construction...
  • Page 30 Fault Management Support ‘2808 EPWM1A EPWM2A ShutDown setCL1 EPWM1B setCL2 EPWM2B setSD ECAP1 Trip Zones: 6 independent zones (TZ1~TZ6) Force High, Low or HiZ on trip One-time trip catastrophic failure Cycle-by-cycle current limit mode TZ1~TZ6 can trigger interrupt...
  • Page 31 Multi-Phase Interleaved (MPI)
  • Page 32 Switching Requirements – MPI • Asymmetrical PWM case • Complementary output generated by dead-band unit • CMPB triggers ADC SOC INIT-time • Period (1,2,3) • CAu Action (1,2,3) • PRD Action (1,2,3) • Phase (2,3) • PRD Interrupt (1) • CBu ADC SOC (1,2,3) •...
  • Page 33 Half H-Bridge (HHB)
  • Page 34 Switching Requirements – HHB • Up/Down Count • Asymmetrical PWM • dead-band on A only • 50 % max Modulation (controlled by CMPA) INIT-time • ZRO Action (A,B) • CAd Action • CAu Action • CBd ADC trigger • CBd ADC trigger •...
  • Page 35 Phase Shifted Full Bridge (PSFB)
  • Page 36 Switching Requirements – PSFB • Asymmetrical PWM • Using dead-band module • Phase (Φ) is the control variable • Duty fixed at ~ 50% • RED / FED control ZVS trans. i.e. via resonance • CMPB can trigger ADC SOC INIT-time •...
  • Page 37 Software Driver Module – ZVSFB...
  • Page 38 Software Driver Module – PFC2PHIL...
  • Page 39 Lab2: PWM Generation / Open-Loop Control Control Buck output voltage using simple PWM duty cycle adjustment without feedback Use CCS watch window and slider button features to conveniently adjust PWM duty cycle...
  • Page 40 Workshop Outline Introduction to Digital Power Supply Design Lab: Exploring the Development Environment Driving the Power Stage with PWM Waveforms Lab: PWM Generation / Open-Loop Control Controlling the Power Stage with Feedback Lab: Closed-Loop Control Tuning the Loop for Good Transient Response Lab: Tuning the Loop Summary and Conclusion...
  • Page 41 Controlling the Power Stage with Feedback Closed-Loop System Block Diagram Analog-to-Digital Converter Module Digital Buck Controller High Resolution PWM Benefits Soft Start – Starting the Loop...
  • Page 42 The “Closed-Loop” Control “PWM” “2P2Z” Duty Vset Uout Power Stage “Loop” “ADC” Feedback Rslt...
  • Page 43 ADC Module Block Diagram Analog MUX ADCINA0 Result MUX ADCINA1 RESULT0 RESULT1 ADCINA7 12-bit A/D RESULT2 Converter ADCINB0 Result ADCINB1 Select RESULT15 Autosequencer ADCINB7 MAX_CONV1 Ch Sel (CONV00) Ch Sel (CONV01) Ch Sel (CONV02) Software Ch Sel (CONV03) ePWM_SOC_A ePWM_SOC_B External Pin Ch Sel (CONV15) (GPIO/XINT2_ADCSOC)
  • Page 44 Digital Control of Power Converter ∆Vc Power Converter Vref ⋅ ∆D ∆Vs Digital Controller E(n) U(n) Gc(z) − − − − − − − − − −...
  • Page 45 Digital Control of Power Converter Steady State Limit Cycle Vo levels (DPWM duty ADC levels error bins ratio steps) Volt +0010 ∆Vs ∆Vc +0001 ∆Vs Vref 0000 ∆Vc -0001 steady state output, limit cycle time Vo levels (DPWM duty ADC levels error bins ratio steps) Volt...
  • Page 46 High Frequency PWM STEP Sysclk PWM resolution = Log SysClk F2808 – SysClk = 100 MHz PWM Freq Regular resolution High resolution (kHz) (bits) (bits) 0.004 14.8 0.005 14.4 0.005 14.2 0.009 13.4 0.014 12.9 0.018 1000 12.4 0.027 1500 11.9 0.036 2000...
  • Page 47 High Resolution PWM (HRPWM) PWM Period Regular Device Clock PWM Step (i.e. 100MHz) (i.e. 10ns) HRPWM divides a clock Calibration Logic tracks the cycle into smaller steps number of Micro Steps per called Micro Steps clock to account for (Step Size ~= 150ps) variations caused by Calibration Logic Temp/Volt/Process...
  • Page 48 Resolution Loss – Low Duty Utilization V o u t Resolution loss in bits V in...
  • Page 49 Benefit of High Resolution PWM Regular PWM (10ns) HiRes PWM (150ps) Limit cycle problem No Limit cycle Edge control is precise Edge jumps around...
  • Page 50 Managing the “Closed-Loop” Fault Trip Dead Band SSartSEQ Vset “PWM” Control Duty “2P2Z” Duty Clamp Delay Uout Slope Target Open/Closed Loop Coeff set 3 “ADC” Coeff set 2 Coeff - B2 Coeff set 1 Coeff - B2 Feedback Coeff - B1 Coeff - B2 Rslt Coeff - B1...
  • Page 51 Simple User Interface Control...
  • Page 52 Soft-Start and Sequencing Multi V...
  • Page 53 Example: Closed-Loop Control Regulate the Buck output by using Voltage Mode Control (VMC) with closed-loop feedback Soft-start and sequencing function used to ensure an “orderly” voltage ramp-up/down Soft-start profile and target voltage is conveniently adjusted by using the CCS watch window and slider buttons feature...
  • Page 54 Workshop Outline Introduction to Digital Power Supply Design Lab: Exploring the Development Environment Driving the Power Stage with PWM Waveforms Lab: PWM Generation / Open-Loop Control Controlling the Power Stage with Feedback Lab: Closed-Loop Control Tuning the Loop for Good Transient Response Lab: Tuning the Loop Summary and Conclusion...
  • Page 55 Tuning the Loop for Good Transient Response Digital Power Supply Control Theory Intuitive Loop Tuning – “Visually without Math” Active Load Feature of the Power EVM Multi-Loop Control...
  • Page 56 The Digital Control System Digital Processor G(s) e(kt) r(t) c(t) Controller Actuator Process D(z) Sensor Advantages Considerations • Immunity from environmental effects • Sample rate • Advanced control strategies possible • Quantization • Immunity from component errors • Ease of programming •...
  • Page 57 PID Control Review ∫ = Proportional gain = Integral gain = Derivative gain Usually written in “parallel” form: ∫ e(t) y(t)           Proportional term controls loop gain Integral action increases low frequency gain and reduces/eliminates steady state errors Derivative action adds phase lead which improves stability and increases system bandwidth...
  • Page 58 Tuning the Step Response Performance of the control loop can be determined from the output response to a change in load Acceptable response might be specified in terms of... Peak overshoot Time to settle to within specified error band We will adjust PID coefficients to optimise our digital controller...
  • Page 59 Loop Tuning – Good First Step − − − −...
  • Page 60 PID – Intuitive / Interactive We can also write the controller in transfer function form: U(z) *z + B ------ = ------------------------- = ---------------------- E(z) 1 - z – z Compare with the General 2P2Z transfer function: U(z) *z + B ------ = --------------------------- = ---------------------- E(z) 1 + A...
  • Page 61 Control Law Computation − − − − ; e(n)=Vref-Vout MOVU ACC,@Vref SUBU ACC,*XAR2++ ACC,#8 ; ACC=e(n) (Q24) MOVL @VCNTL_DBUFF+4,ACC DBUFF U(n) ZAPA ; Voltage control law XAR7 U(n-1) MOVL XT,@VCNTL_DBUFF+8 ; XT=e(n-2) QMPYAL P,XT,*XAR7++ ; b2*e(n-2) U(n-2) MOVDL XT,@VCNTL_DBUFF+6 ; XT=e(n-1), e(n-2)=e(n-1) QMPYAL P,XT,*XAR7++ ;...
  • Page 62 Type II Controller         B o d e D ia g r a m Ω Ω - 1 0 - 2 0 - 4 5 - 9 0 F r e q u e n c y ( r a d / s e c )
  • Page 63 Digital Type II Controller − − DRIVER − − DIGITAL PROCESSOR CONTROLLER B o d e D ia g r a m 1 0 0 03632 - 2 0 3391 - 4 5 (Tustin’s transform, T = 1 us) - 9 0 F r e q u e n c y ( r a d /s e c )
  • Page 64 Type III Controller COMPARATOR DRIVER     CONTROLLER                             B o d e D ia g r a m Ω...
  • Page 65 Digital Type III Controller − − − − DRIVER − − − DIGITAL PROCESSOR CONTROLLER B o d e D ia g r a m 1 0 0 2689 - 4 5 (Tustin’s transform, T = 1 us) - 9 0 F r e q u e n c y ( r a d /s e c )
  • Page 66 2-Channel Buck EVM Active Volt Phase Links TI PowerTrain Load Meter LEDs PTD08A010W 10A module Current meas. Temp meas Over Current Prot. Over Current Flag No Heat-sink needed...
  • Page 67 2-Channel Buck EVM Schematic...
  • Page 68 Lab4: Tuning the Loop Tune closed-loop Buck power stage for improved transient performance using visual “trial and error” (rather than mathematical approach) The 2-channel Buck EVM has an active load circuit when enabled by software provides a repetitive step change in load CCS graph window feature used to view the transient in real-time Transient response can be modified directly until the desired improvement is achieved by adjusting P, I, D sliders...
  • Page 69 Multi-Loop Control...
  • Page 70 PFC (2PHIL) Software Control Flow...
  • Page 71 DC-DC (ZVSFB) Software Control Flow...
  • Page 72 CPU Bandwidth Utilization MIPS = 100 # inst / us = 100 PWM (kHz) = 200 # TS = 4 # inst / time slice = 500 PWM (bits) = 9.0 S. rate = 200 Sampling period = 5.0 Rate Function / Activity # Cyc Tot.
  • Page 73 Workshop Outline Introduction to Digital Power Supply Design Lab: Exploring the Development Environment Driving the Power Stage with PWM Waveforms Lab: PWM Generation / Open-Loop Control Controlling the Power Stage with Feedback Lab: Closed-Loop Control Tuning the Loop for Good Transient Response Lab: Tuning the Loop Summary and Conclusion...
  • Page 74 Summary and Conclusion Review of Workshop Topics and Exercises TI Digital Power Products C2000 Digital Signal Controller Family UCD9xxx Digital Power Controller Family Where to Find More Information...
  • Page 75 Workshop Topics and Exercises Review C28x DSC family provides ideal controller for Digital Power Supply design Scalable ePWM peripherals, ADC and fault management support Code Composer Studio, DPS Library and TI Buck EVM Controlled Buck output voltage using PWM waveform and duty cycle without feedback Controlled Buck output using Voltage Mode Control with feedback...
  • Page 76 TI’s Digital Power Controller Portfolio of Solutions Fully-Programmable / F283xx Control Focused F281x F282xx F280xx UCD922x UCD911x UCD924x Power-Optimized Controllers UCD9080 System Complexity...
  • Page 77 • TMS320C28x 32-bit controller • Single Phase: UCD3xxx solutions for green energy (solar, • Secondary: wind, fuel cells), UPS, and battery • C2000 Voltage mode & current mode control management • UCD3x Voltage mode control • Primary plus Secondary: C2000 Non-Isolated DC/DC •...
  • Page 78 C2000 Family Roadmap Future Future C28xxx C28xxx F283xx F283xx 300 MFLOPS 300 MFLOPS FPU, DMA FPU, DMA F282xx F282xx 150 MHz 150 MHz F281x F281x 150 MHz 150 MHz Future 8 Devices Future 8 Devices C28xxx C28xxx F280xx F280xx 100 MHz...
  • Page 79 TMS320F280xx High Performance DSP (C28x Core) Code security 100 MIPS performance 32-256 4-16 Single cycle 32 x32-bit MAC (or dual 16 x16 MAC) Boot Flash ePWM Very Fast Interrupt Response Single cycle read-modified-write eCAP Memory Sub-System Memory Bus eQEP Fast program execution out of both RAM and Flash memory 12-bit ADC 80 MIPS with Flash Acceleration Technology...
  • Page 80 The First Floating-Point DSCs Processor Performance Code security TMS320F28335 300 MFLOPS at 150MHz 68 KB 512 KB Single-cycle 32-bit MAC Boot Flash 6-channel DMA support for EMIF, 18 PWM (6 HRPWM) ADC, McBSP Memory Bus 6 CAP Memory Three memory options with up to 2 QEP 512KB flash and 68KB RAM Interrupt Management...
  • Page 81 C2000 Digital Power Tools • F28x-based DIMM controller cards • Standard 100-pin interface to all I/Os • Compatible with all Power EVMS • Available for $50-$79(TBD) • 2-rail DC/DC EVM • 8-rail DC/DC EVM using TI using TI PowerTrain™ PowerTrain™ modules (10A) modules (10A) •...
  • Page 82 VisSim Graphical Programming for C2000 Model based design for simulation, code generation, and interactive debugging Efficient code generation near hand code quality Automatic code generation for F28xx peripherals: ADC, SCI, SPI, I C, CAN, ePWM, GPIO High speed target acquisition for wave form display on PC Watch ‘how to’...
  • Page 83 UCD9xxx Digital Power Controller Family 4 ind outputs UCD9240 64 & 80 pin 3 ind outputs UCD92xx UCD9230 48 pin 2 ind outputs UCD9220 32 pin 1 output, 2 phase UCD9112 32 pin UCD91xx 1 output, 1 phase UCD9111 32 pin Integration...
  • Page 84 Recommended Next Step: One-day Training Course TMS320C28x 1-Day Workshop Outline - Workshop Introduction - Architecture Overview - Programming Development Environment - Peripheral Register Header Files - Reset, Interrupts and System Initialization - Control Peripherals - IQ Math Library and DSP/BIOS - Flash Programming Introduction to - The Next Step…...
  • Page 85 Recommended Next Step: Multi-day Training Course TMS320C28x Multi-day Workshop Outline - Architectural Overview - Programming Development Environment - Peripheral Register Header Files - Reset and Interrupts - System Initialization - Analog-to-Digital Converter - Control Peripherals - Numerical Concepts and IQmath In-depth - Using DSP/BIOS TMS320F2808...
  • Page 86 For More Information . . . Internet Website: http://www.ti.com FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm Device information my.ti.com Application notes News and events Technical documentation Training Enroll in Technical Training: http://www.ti.com/sc/training USA - Product Information Center ( PIC ) Phone: 800-477-8924 972-644-5580 Email: support@ti.com Information and support for TI Semiconductor products/tools Submit...
  • Page 87 European Product Information Center (EPIC) Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm Phone: Language Number Belgium (English) +32 (0) 27 45 55 32 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 1800 949 0107 (free phone) Italy 79 11 37 (free phone) Netherlands (English)

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