Table 2.9 System Control Instructions - Renesas H8S Series Hardware Manual

Table 2.9 System Control Instructions
Size *
Instruction
TRAPA —
RTE —
SLEEP —
LDC B/W
STC B/W
ANDC B
ORC B
XORC B
NOP —
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Function
Starts trap-instruction exception handling.
Returns from an exception-handling routine.
Causes a transition to a power-down state.
(EAs) → CCR, (EAs) → EXR
Moves the source operand contents or immediate data to CCR or EXR.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically XORs the CCR or EXR contents with immediate data.
PC + 2 → PC
Only increments the program counter.
Rev. 6.00 Mar 15, 2006 page 39 of 570
REJ09B0211-0600
Section 2 CPU