Timing Diagram For Register Setting - Samsung S5PC110 Manual

Risc microprocessor
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S5PC110_UM

2.7.5 TIMING DIAGRAM FOR REGISTER SETTING

The first register setting for frame capture command can happen anytime in the frame period. It is recommended
to first set the VSYNC "L" state, input DMA start "L" state, and then VVALID "H" state. VSYNC and VVALID
information can be read from status SFR. For more information, refer to
All commands (including ImgCptEn) are valid at VSYNC falling edge or VVALID rising edge. Except the first SFR
setting, all commands should be programmed in the Interrupt Service Routine (ISR). Size, image mirror or
rotation, windowing, and zoom in settings are allowed to change during capturing. In case of DMA input mode, all
command should be programmed after the InputDMA and OutputDMA operation ends, as shown in
VSYNC
HREF
INTERRUPT
Image Capture
VVALID
HVALID
INTERRUPT
Image Capture
VSYNC
HREF
INTERRUPT
Image Capture
New Command
Figure 2-13
Memory Storing Style
Reserved
SFR setting
(ImageCptEr)
Reserved
SFR setting
(ImgCptEr)
Frame Capture Start for external camera input
In Capturing
Reserved
New SFR
command
New command valid timing diagram
2 1BCAMERA INTERFACE
Figure
2-14.
Multi frame
capturing
Multi frame
capturing
Figure
2-15.
2-16

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