Motorola PowerQUICC II MPC8280 Series Reference Manual page 396

Message Unit (I O)
2
Bits Name
31 IMC Write 1 to set from PCI.
Write 1 to clear from local processor.
30–0 IDRx Write 1 to set from PCI.
Write 1 to clear from local processor.
9.12.3 I O Unit
2
The Intelligent Input Output specification (I
architecture-independent I/O subsystems to communicate with an OS through an
abstraction layer. The specification is centered around a message passing scheme. An I
embedded peripheral (IOP) is comprised of memory, processor, and input/output device(s).
An IOP dedicates space in its local memory to hold inbound (from the remote host) and
outbound (to the remote host) messages. The space is managed as memory-mapped FIFOs,
with pointers to this memory maintained in hardware.
Messages are made up of frames which are a minimum of 64-bytes in length. The message
frame address (MFA) is the address which points to the first byte of the message frame. The
messages are located in local-system memory. Tracking of the status and location of these
messages is done with four FIFOs (two FIFOs for inbound and two for outbound messages)
also located in local-system memory. Hardware registers inside the PCI bridge's core logic
manage these FIFOs. One FIFO in each queue keeps track of the free MFAs (Free_LIST
FIFO). The other FIFO keeps track of the MFAs which have posted messages (Post_LIST
FIFO). Figure 9-64 shows an example of the message queues, although there is no specific
order that these queues must follow.
9-74
Freescale Semiconductor, Inc.
Table 9-49. IDR Field Descriptions
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Description
Machine check. Writing to this bit will generate a machine
check interrupt to the local processor.
Inbound door bell x, where x is each bit. Writing a bit in this
register from the PCI bus causes an interrupt to be
t
generated through he PCI bridge to the local processor.
O) was established in the industry to allow
2
O
2
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